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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Diff between revs 34 and 35

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Rev 34 Rev 35
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//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
module vl_mux2_andor ( a1, a0, sel, dout);
module vl_mux2_andor ( a1, a0, sel, dout);
parameter width = 32;
parameter width = 32;
parameter nr_of_ports = 2;
localparam nr_of_ports = 2;
input [width-1:0] a1, a0;
input [width-1:0] a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
output [width-1:0] dout;
wire [width-1:0] tmp [nr_of_ports-1:0];
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
integer i;
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// or
// or
assign dout = tmp[1] | tmp[0];
assign dout = tmp[1] | tmp[0];
endmodule
endmodule
module vl_mux3_andor ( a2, a1, a0, sel, dout);
module vl_mux3_andor ( a2, a1, a0, sel, dout);
parameter width = 32;
parameter width = 32;
parameter nr_of_ports = 3;
localparam nr_of_ports = 3;
input [width-1:0] a2, a1, a0;
input [width-1:0] a2, a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
output [width-1:0] dout;
wire [width-1:0] tmp [nr_of_ports-1:0];
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
integer i;
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// or
// or
assign dout = tmp[2] | tmp[1] | tmp[0];
assign dout = tmp[2] | tmp[1] | tmp[0];
endmodule
endmodule
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
parameter width = 32;
parameter width = 32;
parameter nr_of_ports = 4;
localparam nr_of_ports = 4;
input [width-1:0] a3, a2, a1, a0;
input [width-1:0] a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
output [width-1:0] dout;
wire [width-1:0] tmp [nr_of_ports-1:0];
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
integer i;
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// or
// or
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
endmodule
endmodule
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
parameter width = 32;
parameter width = 32;
parameter nr_of_ports = 5;
localparam nr_of_ports = 5;
input [width-1:0] a4, a3, a2, a1, a0;
input [width-1:0] a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
output [width-1:0] dout;
wire [width-1:0] tmp [nr_of_ports-1:0];
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
integer i;
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// or
// or
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
endmodule
endmodule
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
parameter width = 32;
parameter width = 32;
parameter nr_of_ports = 6;
localparam nr_of_ports = 6;
input [width-1:0] a5, a4, a3, a2, a1, a0;
input [width-1:0] a5, a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
output [width-1:0] dout;
wire [width-1:0] tmp [nr_of_ports-1:0];
wire [width-1:0] tmp [nr_of_ports-1:0];
integer i;
integer i;

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