OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Diff between revs 35 and 36

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 35 Rev 36
Line 435... Line 435...
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
module vl_mux_andor ( a, sel, dout);
 
parameter width = 32;
 
parameter nr_of_ports = 4;
 
input [nr_of_ports*width-1:0] a;
 
input [nr_of_ports-1:0] sel;
 
output reg [width-1:0] dout;
 
always @ (a, sel)
 
begin
 
    dout = a[width-1:0] & {width{sel[0]}};
 
    for (i=nr_of_ports-2;i<nr_of_ports;i=i+1)
 
        dout = (a[i*width-1:(i-1)*width] & {width{sel[i]}}) | dout;
 
end
 
endmodule
module vl_mux2_andor ( a1, a0, sel, dout);
module vl_mux2_andor ( a1, a0, sel, dout);
parameter width = 32;
parameter width = 32;
localparam nr_of_ports = 2;
localparam nr_of_ports = 2;
input [width-1:0] a1, a0;
input [width-1:0] a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
output [width-1:0] dout;
wire [width-1:0] tmp [nr_of_ports-1:0];
vl_mux_andor
integer i;
    # ( .width(width), .nr_of_ports(nr_of_ports)
// and
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
assign tmp[0] = {width{sel[0]}} & a0;
/*
assign tmp[1] = {width{sel[1]}} & a1;
wire [width-1:0] tmp [nr_of_ports-1:0];
// or
integer i;
assign dout = tmp[1] | tmp[0];
// and
 
assign tmp[0] = {width{sel[0]}} & a0;
 
assign tmp[1] = {width{sel[1]}} & a1;
 
// or
 
assign dout = tmp[1] | tmp[0];
 
*/
endmodule
endmodule
module vl_mux3_andor ( a2, a1, a0, sel, dout);
module vl_mux3_andor ( a2, a1, a0, sel, dout);
parameter width = 32;
parameter width = 32;
localparam nr_of_ports = 3;
localparam nr_of_ports = 3;
input [width-1:0] a2, a1, a0;
input [width-1:0] a2, a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
output [width-1:0] dout;
wire [width-1:0] tmp [nr_of_ports-1:0];
vl_mux_andor
integer i;
    # ( .width(width), .nr_of_ports(nr_of_ports)
// and
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
assign tmp[0] = {width{sel[0]}} & a0;
/*
assign tmp[1] = {width{sel[1]}} & a1;
wire [width-1:0] tmp [nr_of_ports-1:0];
assign tmp[2] = {width{sel[2]}} & a2;
integer i;
// or
// and
assign dout = tmp[2] | tmp[1] | tmp[0];
assign tmp[0] = {width{sel[0]}} & a0;
 
assign tmp[1] = {width{sel[1]}} & a1;
 
assign tmp[2] = {width{sel[2]}} & a2;
 
// or
 
assign dout = tmp[2] | tmp[1] | tmp[0];
 
*/
endmodule
endmodule
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
parameter width = 32;
parameter width = 32;
localparam nr_of_ports = 4;
localparam nr_of_ports = 4;
input [width-1:0] a3, a2, a1, a0;
input [width-1:0] a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
output [width-1:0] dout;
wire [width-1:0] tmp [nr_of_ports-1:0];
vl_mux_andor
integer i;
    # ( .width(width), .nr_of_ports(nr_of_ports)
// and
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
assign tmp[0] = {width{sel[0]}} & a0;
/*
assign tmp[1] = {width{sel[1]}} & a1;
wire [width-1:0] tmp [nr_of_ports-1:0];
assign tmp[2] = {width{sel[2]}} & a2;
integer i;
assign tmp[3] = {width{sel[3]}} & a3;
// and
// or
assign tmp[0] = {width{sel[0]}} & a0;
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
assign tmp[1] = {width{sel[1]}} & a1;
 
assign tmp[2] = {width{sel[2]}} & a2;
 
assign tmp[3] = {width{sel[3]}} & a3;
 
// or
 
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
 
*/
endmodule
endmodule
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
parameter width = 32;
parameter width = 32;
localparam nr_of_ports = 5;
localparam nr_of_ports = 5;
input [width-1:0] a4, a3, a2, a1, a0;
input [width-1:0] a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
output [width-1:0] dout;
wire [width-1:0] tmp [nr_of_ports-1:0];
vl_mux_andor
integer i;
    # ( .width(width), .nr_of_ports(nr_of_ports)
// and
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
assign tmp[0] = {width{sel[0]}} & a0;
/*
assign tmp[1] = {width{sel[1]}} & a1;
wire [width-1:0] tmp [nr_of_ports-1:0];
assign tmp[2] = {width{sel[2]}} & a2;
integer i;
assign tmp[3] = {width{sel[3]}} & a3;
// and
assign tmp[4] = {width{sel[4]}} & a4;
assign tmp[0] = {width{sel[0]}} & a0;
// or
assign tmp[1] = {width{sel[1]}} & a1;
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
assign tmp[2] = {width{sel[2]}} & a2;
 
assign tmp[3] = {width{sel[3]}} & a3;
 
assign tmp[4] = {width{sel[4]}} & a4;
 
// or
 
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
 
*/
endmodule
endmodule
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
parameter width = 32;
parameter width = 32;
localparam nr_of_ports = 6;
localparam nr_of_ports = 6;
input [width-1:0] a5, a4, a3, a2, a1, a0;
input [width-1:0] a5, a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
output [width-1:0] dout;
wire [width-1:0] tmp [nr_of_ports-1:0];
vl_mux_andor
integer i;
    # ( .width(width), .nr_of_ports(nr_of_ports)
// and
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
assign tmp[0] = {width{sel[0]}} & a0;
/*
assign tmp[1] = {width{sel[1]}} & a1;
wire [width-1:0] tmp [nr_of_ports-1:0];
assign tmp[2] = {width{sel[2]}} & a2;
integer i;
assign tmp[3] = {width{sel[3]}} & a3;
// and
assign tmp[4] = {width{sel[4]}} & a4;
assign tmp[0] = {width{sel[0]}} & a0;
assign tmp[5] = {width{sel[5]}} & a5;
assign tmp[1] = {width{sel[1]}} & a1;
// or
assign tmp[2] = {width{sel[2]}} & a2;
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
assign tmp[3] = {width{sel[3]}} & a3;
 
assign tmp[4] = {width{sel[4]}} & a4;
 
assign tmp[5] = {width{sel[5]}} & a5;
 
// or
 
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
 
*/
endmodule
endmodule
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.