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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Diff between revs 37 and 38

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Rev 37 Rev 38
Line 441... Line 441...
parameter width = 32;
parameter width = 32;
parameter nr_of_ports = 4;
parameter nr_of_ports = 4;
input [nr_of_ports*width-1:0] a;
input [nr_of_ports*width-1:0] a;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output reg [width-1:0] dout;
output reg [width-1:0] dout;
 
integer i,j;
always @ (a, sel)
always @ (a, sel)
begin
begin
    dout = a[width-1:0] & {width{sel[0]}};
    dout = a[width-1:0] & {width{sel[0]}};
    for (i=nr_of_ports-2;i<nr_of_ports;i=i+1)
    for (i=nr_of_ports-2;i<nr_of_ports;i=i+1)
        dout = (a[i*width-1:(i-1)*width] & {width{sel[i]}}) | dout;
        for (j=0;j<32;j=j+1)
 
            dout[j] = (a[(i-1)*width + j] & sel[i]) | dout[j];
end
end
endmodule
endmodule
module vl_mux2_andor ( a1, a0, sel, dout);
module vl_mux2_andor ( a1, a0, sel, dout);
parameter width = 32;
parameter width = 32;
localparam nr_of_ports = 2;
localparam nr_of_ports = 2;
input [width-1:0] a1, a0;
input [width-1:0] a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
output [width-1:0] dout;
vl_mux_andor
vl_mux_andor
    # ( .width(width), .nr_of_ports(nr_of_ports)
    # ( .width(width), .nr_of_ports(nr_of_ports))
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
/*
 
wire [width-1:0] tmp [nr_of_ports-1:0];
 
integer i;
 
// and
 
assign tmp[0] = {width{sel[0]}} & a0;
 
assign tmp[1] = {width{sel[1]}} & a1;
 
// or
 
assign dout = tmp[1] | tmp[0];
 
*/
 
endmodule
endmodule
module vl_mux3_andor ( a2, a1, a0, sel, dout);
module vl_mux3_andor ( a2, a1, a0, sel, dout);
parameter width = 32;
parameter width = 32;
localparam nr_of_ports = 3;
localparam nr_of_ports = 3;
input [width-1:0] a2, a1, a0;
input [width-1:0] a2, a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
output [width-1:0] dout;
vl_mux_andor
vl_mux_andor
    # ( .width(width), .nr_of_ports(nr_of_ports)
    # ( .width(width), .nr_of_ports(nr_of_ports))
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
/*
 
wire [width-1:0] tmp [nr_of_ports-1:0];
 
integer i;
 
// and
 
assign tmp[0] = {width{sel[0]}} & a0;
 
assign tmp[1] = {width{sel[1]}} & a1;
 
assign tmp[2] = {width{sel[2]}} & a2;
 
// or
 
assign dout = tmp[2] | tmp[1] | tmp[0];
 
*/
 
endmodule
endmodule
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
parameter width = 32;
parameter width = 32;
localparam nr_of_ports = 4;
localparam nr_of_ports = 4;
input [width-1:0] a3, a2, a1, a0;
input [width-1:0] a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
output [width-1:0] dout;
vl_mux_andor
vl_mux_andor
    # ( .width(width), .nr_of_ports(nr_of_ports)
    # ( .width(width), .nr_of_ports(nr_of_ports))
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
 
wire [width-1:0] tmp [nr_of_ports-1:0];
 
integer i;
 
// and
 
assign tmp[0] = {width{sel[0]}} & a0;
 
assign tmp[1] = {width{sel[1]}} & a1;
 
assign tmp[2] = {width{sel[2]}} & a2;
 
assign tmp[3] = {width{sel[3]}} & a3;
 
// or
 
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
 
*/
 
endmodule
endmodule
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
parameter width = 32;
parameter width = 32;
localparam nr_of_ports = 5;
localparam nr_of_ports = 5;
input [width-1:0] a4, a3, a2, a1, a0;
input [width-1:0] a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
output [width-1:0] dout;
vl_mux_andor
vl_mux_andor
    # ( .width(width), .nr_of_ports(nr_of_ports)
    # ( .width(width), .nr_of_ports(nr_of_ports))
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
 
wire [width-1:0] tmp [nr_of_ports-1:0];
 
integer i;
 
// and
 
assign tmp[0] = {width{sel[0]}} & a0;
 
assign tmp[1] = {width{sel[1]}} & a1;
 
assign tmp[2] = {width{sel[2]}} & a2;
 
assign tmp[3] = {width{sel[3]}} & a3;
 
assign tmp[4] = {width{sel[4]}} & a4;
 
// or
 
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
 
*/
 
endmodule
endmodule
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
parameter width = 32;
parameter width = 32;
localparam nr_of_ports = 6;
localparam nr_of_ports = 6;
input [width-1:0] a5, a4, a3, a2, a1, a0;
input [width-1:0] a5, a4, a3, a2, a1, a0;
input [nr_of_ports-1:0] sel;
input [nr_of_ports-1:0] sel;
output [width-1:0] dout;
output [width-1:0] dout;
vl_mux_andor
vl_mux_andor
    # ( .width(width), .nr_of_ports(nr_of_ports)
    # ( .width(width), .nr_of_ports(nr_of_ports))
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
/*
 
wire [width-1:0] tmp [nr_of_ports-1:0];
 
integer i;
 
// and
 
assign tmp[0] = {width{sel[0]}} & a0;
 
assign tmp[1] = {width{sel[1]}} & a1;
 
assign tmp[2] = {width{sel[2]}} & a2;
 
assign tmp[3] = {width{sel[3]}} & a3;
 
assign tmp[4] = {width{sel[4]}} & a4;
 
assign tmp[5] = {width{sel[5]}} & a5;
 
// or
 
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
 
*/
 
endmodule
endmodule
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