//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile library, clock and reset ////
|
//// Versatile library, clock and reset ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Logic related to clock and reset ////
|
//// Logic related to clock and reset ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - add more different registers ////
|
//// - add more different registers ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
// Global buffer
|
// Global buffer
|
// usage:
|
// usage:
|
// use to enable global buffers for high fan out signals such as clock and reset
|
// use to enable global buffers for high fan out signals such as clock and reset
|
`timescale 1 ns/100 ps
|
`timescale 1 ns/100 ps
|
// Version: 8.4 8.4.0.33
|
// Version: 8.4 8.4.0.33
|
module gbuf(GL,CLK);
|
module gbuf(GL,CLK);
|
output GL;
|
output GL;
|
input CLK;
|
input CLK;
|
wire GND;
|
wire GND;
|
GND GND_1_net(.Y(GND));
|
GND GND_1_net(.Y(GND));
|
CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
|
CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
|
.DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
|
.DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
|
endmodule
|
endmodule
|
`timescale 1 ns/1 ns
|
`timescale 1 ns/1 ns
|
module vl_gbuf ( i, o);
|
module vl_gbuf ( i, o);
|
input i;
|
input i;
|
output o;
|
output o;
|
`ifdef SIM_GBUF
|
`ifdef SIM_GBUF
|
assign o=i;
|
assign o=i;
|
`else
|
`else
|
gbuf gbuf_i0 ( .CLK(i), .GL(o));
|
gbuf gbuf_i0 ( .CLK(i), .GL(o));
|
`endif
|
`endif
|
endmodule
|
endmodule
|
//ACTEL
|
//ACTEL
|
// sync reset
|
// sync reset
|
// input active lo async reset, normally from external reset generator and/or switch
|
// input active lo async reset, normally from external reset generator and/or switch
|
// output active high global reset sync with two DFFs
|
// output active high global reset sync with two DFFs
|
`timescale 1 ns/100 ps
|
`timescale 1 ns/100 ps
|
module vl_sync_rst ( rst_n_i, rst_o, clk);
|
module vl_sync_rst ( rst_n_i, rst_o, clk);
|
input rst_n_i, clk;
|
input rst_n_i, clk;
|
output rst_o;
|
output rst_o;
|
reg [1:0] tmp;
|
reg [1:0] tmp;
|
always @ (posedge clk or negedge rst_n_i)
|
always @ (posedge clk or negedge rst_n_i)
|
if (!rst_n_i)
|
if (!rst_n_i)
|
tmp <= 2'b11;
|
tmp <= 2'b11;
|
else
|
else
|
tmp <= {1'b0,tmp[1]};
|
tmp <= {1'b0,tmp[1]};
|
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
|
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
|
endmodule
|
endmodule
|
// vl_pll
|
// vl_pll
|
///////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////
|
`timescale 1 ps/1 ps
|
`timescale 1 ps/1 ps
|
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
|
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
|
parameter index = 0;
|
parameter index = 0;
|
parameter number_of_clk = 1;
|
parameter number_of_clk = 1;
|
parameter period_time_0 = 20000;
|
parameter period_time_0 = 20000;
|
parameter period_time_1 = 20000;
|
parameter period_time_1 = 20000;
|
parameter period_time_2 = 20000;
|
parameter period_time_2 = 20000;
|
parameter lock_delay = 2000000;
|
parameter lock_delay = 2000000;
|
input clk_i, rst_n_i;
|
input clk_i, rst_n_i;
|
output lock;
|
output lock;
|
output reg [0:number_of_clk-1] clk_o;
|
output reg [0:number_of_clk-1] clk_o;
|
output [0:number_of_clk-1] rst_o;
|
output [0:number_of_clk-1] rst_o;
|
`ifdef SIM_PLL
|
`ifdef SIM_PLL
|
always
|
always
|
#((period_time_0)/2) clk_o[0] <= (!rst_n_i) ? 0 : ~clk_o[0];
|
#((period_time_0)/2) clk_o[0] <= (!rst_n_i) ? 0 : ~clk_o[0];
|
generate if (number_of_clk > 1)
|
generate if (number_of_clk > 1)
|
always
|
always
|
#((period_time_1)/2) clk_o[1] <= (!rst_n_i) ? 0 : ~clk_o[1];
|
#((period_time_1)/2) clk_o[1] <= (!rst_n_i) ? 0 : ~clk_o[1];
|
endgenerate
|
endgenerate
|
generate if (number_of_clk > 2)
|
generate if (number_of_clk > 2)
|
always
|
always
|
#((period_time_2)/2) clk_o[2] <= (!rst_n_i) ? 0 : ~clk_o[2];
|
#((period_time_2)/2) clk_o[2] <= (!rst_n_i) ? 0 : ~clk_o[2];
|
endgenerate
|
endgenerate
|
genvar i;
|
genvar i;
|
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
|
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
|
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
|
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
|
end
|
end
|
endgenerate
|
endgenerate
|
assign #lock_delay lock = rst_n_i;
|
assign #lock_delay lock = rst_n_i;
|
endmodule
|
endmodule
|
`else
|
`else
|
generate if (number_of_clk==1 & index==0) begin
|
generate if (number_of_clk==1 & index==0) begin
|
pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
|
pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
|
end
|
end
|
endgenerate // index==0
|
endgenerate // index==0
|
generate if (number_of_clk==1 & index==1) begin
|
generate if (number_of_clk==1 & index==1) begin
|
pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
|
pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
|
end
|
end
|
endgenerate // index==1
|
endgenerate // index==1
|
generate if (number_of_clk==1 & index==2) begin
|
generate if (number_of_clk==1 & index==2) begin
|
pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
|
pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
|
end
|
end
|
endgenerate // index==2
|
endgenerate // index==2
|
generate if (number_of_clk==1 & index==3) begin
|
generate if (number_of_clk==1 & index==3) begin
|
pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
|
pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
|
end
|
end
|
endgenerate // index==0
|
endgenerate // index==0
|
generate if (number_of_clk==2 & index==0) begin
|
generate if (number_of_clk==2 & index==0) begin
|
pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
|
pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
|
end
|
end
|
endgenerate // index==0
|
endgenerate // index==0
|
generate if (number_of_clk==2 & index==1) begin
|
generate if (number_of_clk==2 & index==1) begin
|
pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
|
pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
|
end
|
end
|
endgenerate // index==1
|
endgenerate // index==1
|
generate if (number_of_clk==2 & index==2) begin
|
generate if (number_of_clk==2 & index==2) begin
|
pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
|
pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
|
end
|
end
|
endgenerate // index==2
|
endgenerate // index==2
|
generate if (number_of_clk==2 & index==3) begin
|
generate if (number_of_clk==2 & index==3) begin
|
pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
|
pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
|
end
|
end
|
endgenerate // index==0
|
endgenerate // index==0
|
generate if (number_of_clk==3 & index==0) begin
|
generate if (number_of_clk==3 & index==0) begin
|
pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
|
pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
|
end
|
end
|
endgenerate // index==0
|
endgenerate // index==0
|
generate if (number_of_clk==3 & index==1) begin
|
generate if (number_of_clk==3 & index==1) begin
|
pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
|
pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
|
end
|
end
|
endgenerate // index==1
|
endgenerate // index==1
|
generate if (number_of_clk==3 & index==2) begin
|
generate if (number_of_clk==3 & index==2) begin
|
pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
|
pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
|
end
|
end
|
endgenerate // index==2
|
endgenerate // index==2
|
generate if (number_of_clk==3 & index==3) begin
|
generate if (number_of_clk==3 & index==3) begin
|
pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
|
pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
|
end
|
end
|
endgenerate // index==0
|
endgenerate // index==0
|
genvar i;
|
genvar i;
|
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
|
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
|
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
|
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
|
end
|
end
|
endgenerate
|
endgenerate
|
endmodule
|
endmodule
|
`endif
|
`endif
|
///////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////
|
//actel
|
//actel
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile library, registers ////
|
//// Versatile library, registers ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Different type of registers ////
|
//// Different type of registers ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - add more different registers ////
|
//// - add more different registers ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
module vl_dff ( d, q, clk, rst);
|
module vl_dff ( d, q, clk, rst);
|
parameter width = 1;
|
parameter width = 1;
|
parameter reset_value = 0;
|
parameter reset_value = 0;
|
input [width-1:0] d;
|
input [width-1:0] d;
|
input clk, rst;
|
input clk, rst;
|
output reg [width-1:0] q;
|
output reg [width-1:0] q;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= reset_value;
|
q <= reset_value;
|
else
|
else
|
q <= d;
|
q <= d;
|
endmodule
|
endmodule
|
module vl_dff_array ( d, q, clk, rst);
|
module vl_dff_array ( d, q, clk, rst);
|
parameter width = 1;
|
parameter width = 1;
|
parameter depth = 2;
|
parameter depth = 2;
|
parameter reset_value = 1'b0;
|
parameter reset_value = 1'b0;
|
input [width-1:0] d;
|
input [width-1:0] d;
|
input clk, rst;
|
input clk, rst;
|
output [width-1:0] q;
|
output [width-1:0] q;
|
reg [0:depth-1] q_tmp [width-1:0];
|
reg [0:depth-1] q_tmp [width-1:0];
|
integer i;
|
integer i;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst) begin
|
if (rst) begin
|
for (i=0;i<depth;i=i+1)
|
for (i=0;i<depth;i=i+1)
|
q_tmp[i] <= {width{reset_value}};
|
q_tmp[i] <= {width{reset_value}};
|
end else begin
|
end else begin
|
q_tmp[0] <= d;
|
q_tmp[0] <= d;
|
for (i=1;i<depth;i=i+1)
|
for (i=1;i<depth;i=i+1)
|
q_tmp[i] <= q_tmp[i-1];
|
q_tmp[i] <= q_tmp[i-1];
|
end
|
end
|
assign q = q_tmp[depth-1];
|
assign q = q_tmp[depth-1];
|
endmodule
|
endmodule
|
module vl_dff_ce ( d, ce, q, clk, rst);
|
module vl_dff_ce ( d, ce, q, clk, rst);
|
parameter width = 1;
|
parameter width = 1;
|
parameter reset_value = 0;
|
parameter reset_value = 0;
|
input [width-1:0] d;
|
input [width-1:0] d;
|
input ce, clk, rst;
|
input ce, clk, rst;
|
output reg [width-1:0] q;
|
output reg [width-1:0] q;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= reset_value;
|
q <= reset_value;
|
else
|
else
|
if (ce)
|
if (ce)
|
q <= d;
|
q <= d;
|
endmodule
|
endmodule
|
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
|
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
|
parameter width = 1;
|
parameter width = 1;
|
parameter reset_value = 0;
|
parameter reset_value = 0;
|
input [width-1:0] d;
|
input [width-1:0] d;
|
input ce, clear, clk, rst;
|
input ce, clear, clk, rst;
|
output reg [width-1:0] q;
|
output reg [width-1:0] q;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= reset_value;
|
q <= reset_value;
|
else
|
else
|
if (ce)
|
if (ce)
|
if (clear)
|
if (clear)
|
q <= {width{1'b0}};
|
q <= {width{1'b0}};
|
else
|
else
|
q <= d;
|
q <= d;
|
endmodule
|
endmodule
|
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
|
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
|
parameter width = 1;
|
parameter width = 1;
|
parameter reset_value = 0;
|
parameter reset_value = 0;
|
input [width-1:0] d;
|
input [width-1:0] d;
|
input ce, set, clk, rst;
|
input ce, set, clk, rst;
|
output reg [width-1:0] q;
|
output reg [width-1:0] q;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= reset_value;
|
q <= reset_value;
|
else
|
else
|
if (ce)
|
if (ce)
|
if (set)
|
if (set)
|
q <= {width{1'b1}};
|
q <= {width{1'b1}};
|
else
|
else
|
q <= d;
|
q <= d;
|
endmodule
|
endmodule
|
module vl_spr ( sp, r, q, clk, rst);
|
module vl_spr ( sp, r, q, clk, rst);
|
parameter width = 1;
|
parameter width = 1;
|
parameter reset_value = 0;
|
parameter reset_value = 0;
|
input sp, r;
|
input sp, r;
|
output reg q;
|
output reg q;
|
input clk, rst;
|
input clk, rst;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= reset_value;
|
q <= reset_value;
|
else
|
else
|
if (sp)
|
if (sp)
|
q <= 1'b1;
|
q <= 1'b1;
|
else if (r)
|
else if (r)
|
q <= 1'b0;
|
q <= 1'b0;
|
endmodule
|
endmodule
|
module vl_srp ( s, rp, q, clk, rst);
|
module vl_srp ( s, rp, q, clk, rst);
|
parameter width = 1;
|
parameter width = 1;
|
parameter reset_value = 0;
|
parameter reset_value = 0;
|
input s, rp;
|
input s, rp;
|
output reg q;
|
output reg q;
|
input clk, rst;
|
input clk, rst;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= reset_value;
|
q <= reset_value;
|
else
|
else
|
if (rp)
|
if (rp)
|
q <= 1'b0;
|
q <= 1'b0;
|
else if (s)
|
else if (s)
|
q <= 1'b1;
|
q <= 1'b1;
|
endmodule
|
endmodule
|
module vl_dff_sr ( aclr, aset, clock, data, q);
|
module vl_dff_sr ( aclr, aset, clock, data, q);
|
input aclr;
|
input aclr;
|
input aset;
|
input aset;
|
input clock;
|
input clock;
|
input data;
|
input data;
|
output reg q;
|
output reg q;
|
always @ (posedge clock or posedge aclr or posedge aset)
|
always @ (posedge clock or posedge aclr or posedge aset)
|
if (aclr)
|
if (aclr)
|
q <= 1'b0;
|
q <= 1'b0;
|
else if (aset)
|
else if (aset)
|
q <= 1'b1;
|
q <= 1'b1;
|
else
|
else
|
q <= data;
|
q <= data;
|
endmodule
|
endmodule
|
// LATCH
|
// LATCH
|
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
|
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
|
module latch ( d, le, q, clk);
|
module vl_latch ( d, le, q, clk);
|
input d, le;
|
input d, le;
|
output q;
|
output q;
|
input clk;/*
|
input clk;/*
|
always @ (posedge direction_set or posedge direction_clr)
|
always @ (posedge direction_set or posedge direction_clr)
|
if (direction_clr)
|
if (direction_clr)
|
direction <= going_empty;
|
direction <= going_empty;
|
else
|
else
|
direction <= going_full;*/
|
direction <= going_full;*/
|
endmodule
|
endmodule
|
module vl_shreg ( d, q, clk, rst);
|
module vl_shreg ( d, q, clk, rst);
|
parameter depth = 10;
|
parameter depth = 10;
|
input d;
|
input d;
|
output q;
|
output q;
|
input clk, rst;
|
input clk, rst;
|
reg [1:depth] dffs;
|
reg [1:depth] dffs;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
dffs <= {depth{1'b0}};
|
dffs <= {depth{1'b0}};
|
else
|
else
|
dffs <= {d,dffs[1:depth-1]};
|
dffs <= {d,dffs[1:depth-1]};
|
assign q = dffs[depth];
|
assign q = dffs[depth];
|
endmodule
|
endmodule
|
module vl_shreg_ce ( d, ce, q, clk, rst);
|
module vl_shreg_ce ( d, ce, q, clk, rst);
|
parameter depth = 10;
|
parameter depth = 10;
|
input d, ce;
|
input d, ce;
|
output q;
|
output q;
|
input clk, rst;
|
input clk, rst;
|
reg [1:depth] dffs;
|
reg [1:depth] dffs;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
dffs <= {depth{1'b0}};
|
dffs <= {depth{1'b0}};
|
else
|
else
|
if (ce)
|
if (ce)
|
dffs <= {d,dffs[1:depth-1]};
|
dffs <= {d,dffs[1:depth-1]};
|
assign q = dffs[depth];
|
assign q = dffs[depth];
|
endmodule
|
endmodule
|
module vl_delay ( d, q, clk, rst);
|
module vl_delay ( d, q, clk, rst);
|
parameter depth = 10;
|
parameter depth = 10;
|
input d;
|
input d;
|
output q;
|
output q;
|
input clk, rst;
|
input clk, rst;
|
reg [1:depth] dffs;
|
reg [1:depth] dffs;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
dffs <= {depth{1'b0}};
|
dffs <= {depth{1'b0}};
|
else
|
else
|
dffs <= {d,dffs[1:depth-1]};
|
dffs <= {d,dffs[1:depth-1]};
|
assign q = dffs[depth];
|
assign q = dffs[depth];
|
endmodule
|
endmodule
|
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
|
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
|
parameter depth = 10;
|
parameter depth = 10;
|
input d;
|
input d;
|
output q, emptyflag;
|
output q, emptyflag;
|
input clk, rst;
|
input clk, rst;
|
reg [1:depth] dffs;
|
reg [1:depth] dffs;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
dffs <= {depth{1'b0}};
|
dffs <= {depth{1'b0}};
|
else
|
else
|
dffs <= {d,dffs[1:depth-1]};
|
dffs <= {d,dffs[1:depth-1]};
|
assign q = dffs[depth];
|
assign q = dffs[depth];
|
assign emptyflag = !(|dffs);
|
assign emptyflag = !(|dffs);
|
endmodule
|
endmodule
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Logic functions ////
|
//// Logic functions ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Logic functions such as multiplexers ////
|
//// Logic functions such as multiplexers ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - ////
|
//// - ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
module vl_mux_andor ( a, sel, dout);
|
module vl_mux_andor ( a, sel, dout);
|
parameter width = 32;
|
parameter width = 32;
|
parameter nr_of_ports = 4;
|
parameter nr_of_ports = 4;
|
input [nr_of_ports*width-1:0] a;
|
input [nr_of_ports*width-1:0] a;
|
input [nr_of_ports-1:0] sel;
|
input [nr_of_ports-1:0] sel;
|
output reg [width-1:0] dout;
|
output reg [width-1:0] dout;
|
integer i,j;
|
integer i,j;
|
always @ (a, sel)
|
always @ (a, sel)
|
begin
|
begin
|
dout = a[width-1:0] & {width{sel[0]}};
|
dout = a[width-1:0] & {width{sel[0]}};
|
for (i=nr_of_ports-2;i<nr_of_ports;i=i+1)
|
for (i=nr_of_ports-2;i<nr_of_ports;i=i+1)
|
for (j=0;j<32;j=j+1)
|
for (j=0;j<32;j=j+1)
|
dout[j] = (a[(i-1)*width + j] & sel[i]) | dout[j];
|
dout[j] = (a[(i-1)*width + j] & sel[i]) | dout[j];
|
end
|
end
|
endmodule
|
endmodule
|
module vl_mux2_andor ( a1, a0, sel, dout);
|
module vl_mux2_andor ( a1, a0, sel, dout);
|
parameter width = 32;
|
parameter width = 32;
|
localparam nr_of_ports = 2;
|
localparam nr_of_ports = 2;
|
input [width-1:0] a1, a0;
|
input [width-1:0] a1, a0;
|
input [nr_of_ports-1:0] sel;
|
input [nr_of_ports-1:0] sel;
|
output [width-1:0] dout;
|
output [width-1:0] dout;
|
vl_mux_andor
|
vl_mux_andor
|
# ( .width(width), .nr_of_ports(nr_of_ports))
|
# ( .width(width), .nr_of_ports(nr_of_ports))
|
mux0( .a({a1,a0}), .sel(sel), .dout(dout));
|
mux0( .a({a1,a0}), .sel(sel), .dout(dout));
|
endmodule
|
endmodule
|
module vl_mux3_andor ( a2, a1, a0, sel, dout);
|
module vl_mux3_andor ( a2, a1, a0, sel, dout);
|
parameter width = 32;
|
parameter width = 32;
|
localparam nr_of_ports = 3;
|
localparam nr_of_ports = 3;
|
input [width-1:0] a2, a1, a0;
|
input [width-1:0] a2, a1, a0;
|
input [nr_of_ports-1:0] sel;
|
input [nr_of_ports-1:0] sel;
|
output [width-1:0] dout;
|
output [width-1:0] dout;
|
vl_mux_andor
|
vl_mux_andor
|
# ( .width(width), .nr_of_ports(nr_of_ports))
|
# ( .width(width), .nr_of_ports(nr_of_ports))
|
mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
|
mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
|
endmodule
|
endmodule
|
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
|
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
|
parameter width = 32;
|
parameter width = 32;
|
localparam nr_of_ports = 4;
|
localparam nr_of_ports = 4;
|
input [width-1:0] a3, a2, a1, a0;
|
input [width-1:0] a3, a2, a1, a0;
|
input [nr_of_ports-1:0] sel;
|
input [nr_of_ports-1:0] sel;
|
output [width-1:0] dout;
|
output [width-1:0] dout;
|
vl_mux_andor
|
vl_mux_andor
|
# ( .width(width), .nr_of_ports(nr_of_ports))
|
# ( .width(width), .nr_of_ports(nr_of_ports))
|
mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
|
mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
|
endmodule
|
endmodule
|
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
|
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
|
parameter width = 32;
|
parameter width = 32;
|
localparam nr_of_ports = 5;
|
localparam nr_of_ports = 5;
|
input [width-1:0] a4, a3, a2, a1, a0;
|
input [width-1:0] a4, a3, a2, a1, a0;
|
input [nr_of_ports-1:0] sel;
|
input [nr_of_ports-1:0] sel;
|
output [width-1:0] dout;
|
output [width-1:0] dout;
|
vl_mux_andor
|
vl_mux_andor
|
# ( .width(width), .nr_of_ports(nr_of_ports))
|
# ( .width(width), .nr_of_ports(nr_of_ports))
|
mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
|
mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
|
endmodule
|
endmodule
|
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
|
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
|
parameter width = 32;
|
parameter width = 32;
|
localparam nr_of_ports = 6;
|
localparam nr_of_ports = 6;
|
input [width-1:0] a5, a4, a3, a2, a1, a0;
|
input [width-1:0] a5, a4, a3, a2, a1, a0;
|
input [nr_of_ports-1:0] sel;
|
input [nr_of_ports-1:0] sel;
|
output [width-1:0] dout;
|
output [width-1:0] dout;
|
vl_mux_andor
|
vl_mux_andor
|
# ( .width(width), .nr_of_ports(nr_of_ports))
|
# ( .width(width), .nr_of_ports(nr_of_ports))
|
mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
|
mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
|
endmodule
|
endmodule
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile counter ////
|
//// Versatile counter ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// counter ////
|
//// counter ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - add LFSR with more taps ////
|
//// - add LFSR with more taps ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
// binary counter
|
// binary counter
|
module vl_cnt_bin ( q, rst, clk);
|
module vl_cnt_bin_ce (
|
parameter length = 4;
|
cke, q, rst, clk);
|
output [length:1] q;
|
|
input rst;
|
|
input clk;
|
|
parameter clear_value = 0;
|
|
parameter set_value = 1;
|
|
parameter wrap_value = 0;
|
|
parameter level1_value = 15;
|
|
reg [length:1] qi;
|
|
wire [length:1] q_next;
|
|
assign q_next = qi + {{length-1{1'b0}},1'b1};
|
|
always @ (posedge clk or posedge rst)
|
|
if (rst)
|
|
qi <= {length{1'b0}};
|
|
else
|
|
qi <= q_next;
|
|
assign q = qi;
|
|
endmodule
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Versatile counter ////
|
|
//// ////
|
|
//// Description ////
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
|
//// counter ////
|
|
//// ////
|
|
//// To Do: ////
|
|
//// - add LFSR with more taps ////
|
|
//// ////
|
|
//// Author(s): ////
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
|
//// ORSoC AB ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
|
//// ////
|
|
//// This source file may be used and distributed without ////
|
|
//// restriction provided that this copyright statement is not ////
|
|
//// removed from the file and that any derivative work contains ////
|
|
//// the original copyright notice and the associated disclaimer. ////
|
|
//// ////
|
|
//// This source file is free software; you can redistribute it ////
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
|
//// Public License as published by the Free Software Foundation; ////
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
|
//// later version. ////
|
|
//// ////
|
|
//// This source is distributed in the hope that it will be ////
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
|
//// details. ////
|
|
//// ////
|
|
//// You should have received a copy of the GNU Lesser General ////
|
|
//// Public License along with this source; if not, download it ////
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
// binary counter
|
|
module vl_cnt_bin_clear ( clear, q, rst, clk);
|
|
parameter length = 4;
|
|
input clear;
|
|
output [length:1] q;
|
|
input rst;
|
|
input clk;
|
|
parameter clear_value = 0;
|
|
parameter set_value = 1;
|
|
parameter wrap_value = 0;
|
|
parameter level1_value = 15;
|
|
reg [length:1] qi;
|
|
wire [length:1] q_next;
|
|
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
|
|
always @ (posedge clk or posedge rst)
|
|
if (rst)
|
|
qi <= {length{1'b0}};
|
|
else
|
|
qi <= q_next;
|
|
assign q = qi;
|
|
endmodule
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Versatile counter ////
|
|
//// ////
|
|
//// Description ////
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
|
//// counter ////
|
|
//// ////
|
|
//// To Do: ////
|
|
//// - add LFSR with more taps ////
|
|
//// ////
|
|
//// Author(s): ////
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
|
//// ORSoC AB ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
|
//// ////
|
|
//// This source file may be used and distributed without ////
|
|
//// restriction provided that this copyright statement is not ////
|
|
//// removed from the file and that any derivative work contains ////
|
|
//// the original copyright notice and the associated disclaimer. ////
|
|
//// ////
|
|
//// This source file is free software; you can redistribute it ////
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
|
//// Public License as published by the Free Software Foundation; ////
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
|
//// later version. ////
|
|
//// ////
|
|
//// This source is distributed in the hope that it will be ////
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
|
//// details. ////
|
|
//// ////
|
|
//// You should have received a copy of the GNU Lesser General ////
|
|
//// Public License along with this source; if not, download it ////
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
// binary counter
|
|
module vl_cnt_bin_ce ( cke, q, rst, clk);
|
|
parameter length = 4;
|
|
input cke;
|
|
output [length:1] q;
|
|
input rst;
|
|
input clk;
|
|
parameter clear_value = 0;
|
|
parameter set_value = 1;
|
|
parameter wrap_value = 0;
|
|
parameter level1_value = 15;
|
|
reg [length:1] qi;
|
|
wire [length:1] q_next;
|
|
assign q_next = qi + {{length-1{1'b0}},1'b1};
|
|
always @ (posedge clk or posedge rst)
|
|
if (rst)
|
|
qi <= {length{1'b0}};
|
|
else
|
|
if (cke)
|
|
qi <= q_next;
|
|
assign q = qi;
|
|
endmodule
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Versatile counter ////
|
|
//// ////
|
|
//// Description ////
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
|
//// counter ////
|
|
//// ////
|
|
//// To Do: ////
|
|
//// - add LFSR with more taps ////
|
|
//// ////
|
|
//// Author(s): ////
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
|
//// ORSoC AB ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
|
//// ////
|
|
//// This source file may be used and distributed without ////
|
|
//// restriction provided that this copyright statement is not ////
|
|
//// removed from the file and that any derivative work contains ////
|
|
//// the original copyright notice and the associated disclaimer. ////
|
|
//// ////
|
|
//// This source file is free software; you can redistribute it ////
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
|
//// Public License as published by the Free Software Foundation; ////
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
|
//// later version. ////
|
|
//// ////
|
|
//// This source is distributed in the hope that it will be ////
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
|
//// details. ////
|
|
//// ////
|
|
//// You should have received a copy of the GNU Lesser General ////
|
|
//// Public License along with this source; if not, download it ////
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
// binary counter
|
|
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
|
|
parameter length = 4;
|
|
input clear;
|
|
input cke;
|
|
output [length:1] q;
|
|
input rst;
|
|
input clk;
|
|
parameter clear_value = 0;
|
|
parameter set_value = 1;
|
|
parameter wrap_value = 0;
|
|
parameter level1_value = 15;
|
|
reg [length:1] qi;
|
|
wire [length:1] q_next;
|
|
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
|
|
always @ (posedge clk or posedge rst)
|
|
if (rst)
|
|
qi <= {length{1'b0}};
|
|
else
|
|
if (cke)
|
|
qi <= q_next;
|
|
assign q = qi;
|
|
endmodule
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Versatile counter ////
|
|
//// ////
|
|
//// Description ////
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
|
//// counter ////
|
|
//// ////
|
|
//// To Do: ////
|
|
//// - add LFSR with more taps ////
|
|
//// ////
|
|
//// Author(s): ////
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
|
//// ORSoC AB ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
|
//// ////
|
|
//// This source file may be used and distributed without ////
|
|
//// restriction provided that this copyright statement is not ////
|
|
//// removed from the file and that any derivative work contains ////
|
|
//// the original copyright notice and the associated disclaimer. ////
|
|
//// ////
|
|
//// This source file is free software; you can redistribute it ////
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
|
//// Public License as published by the Free Software Foundation; ////
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
|
//// later version. ////
|
|
//// ////
|
|
//// This source is distributed in the hope that it will be ////
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
|
//// details. ////
|
|
//// ////
|
|
//// You should have received a copy of the GNU Lesser General ////
|
|
//// Public License along with this source; if not, download it ////
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
// binary counter
|
|
module vl_cnt_bin_ce_clear_l1_l2 ( clear, cke, q, level1, level2, rst, clk);
|
|
parameter length = 4;
|
|
input clear;
|
|
input cke;
|
|
output [length:1] q;
|
|
output reg level1;
|
|
output reg level2;
|
|
input rst;
|
|
input clk;
|
|
parameter clear_value = 0;
|
|
parameter set_value = 1;
|
|
parameter wrap_value = 15;
|
|
parameter level1_value = 8;
|
|
parameter level2_value = 15;
|
|
wire rew;
|
|
assign rew = 1'b0;
|
|
reg [length:1] qi;
|
|
wire [length:1] q_next;
|
|
assign q_next = clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
|
|
always @ (posedge clk or posedge rst)
|
|
if (rst)
|
|
qi <= {length{1'b0}};
|
|
else
|
|
if (cke)
|
|
qi <= q_next;
|
|
assign q = qi;
|
|
always @ (posedge clk or posedge rst)
|
|
if (rst)
|
|
level1 <= 1'b0;
|
|
else
|
|
if (cke)
|
|
if (clear)
|
|
level1 <= 1'b0;
|
|
else if (q_next == level1_value)
|
|
level1 <= 1'b1;
|
|
else if (qi == level1_value & rew)
|
|
level1 <= 1'b0;
|
|
always @ (posedge clk or posedge rst)
|
|
if (rst)
|
|
level2 <= 1'b0;
|
|
else
|
|
if (cke)
|
|
if (clear)
|
|
level2 <= 1'b0;
|
|
else if (q_next == level2_value)
|
|
level2 <= 1'b1;
|
|
else if (qi == level2_value & rew)
|
|
level2 <= 1'b0;
|
|
endmodule
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Versatile counter ////
|
|
//// ////
|
|
//// Description ////
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
|
//// counter ////
|
|
//// ////
|
|
//// To Do: ////
|
|
//// - add LFSR with more taps ////
|
|
//// ////
|
|
//// Author(s): ////
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
|
//// ORSoC AB ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
|
//// ////
|
|
//// This source file may be used and distributed without ////
|
|
//// restriction provided that this copyright statement is not ////
|
|
//// removed from the file and that any derivative work contains ////
|
|
//// the original copyright notice and the associated disclaimer. ////
|
|
//// ////
|
|
//// This source file is free software; you can redistribute it ////
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
|
//// Public License as published by the Free Software Foundation; ////
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
|
//// later version. ////
|
|
//// ////
|
|
//// This source is distributed in the hope that it will be ////
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
|
//// details. ////
|
|
//// ////
|
|
//// You should have received a copy of the GNU Lesser General ////
|
|
//// Public License along with this source; if not, download it ////
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
// binary counter
|
|
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
|
|
parameter length = 4;
|
|
input clear;
|
|
input set;
|
|
input cke;
|
|
input rew;
|
|
output [length:1] q;
|
|
input rst;
|
|
input clk;
|
|
parameter clear_value = 0;
|
|
parameter set_value = 1;
|
|
parameter wrap_value = 0;
|
|
parameter level1_value = 15;
|
|
reg [length:1] qi;
|
|
wire [length:1] q_next, q_next_fw, q_next_rew;
|
|
assign q_next_fw = clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
|
|
assign q_next_rew = clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
|
|
assign q_next = rew ? q_next_rew : q_next_fw;
|
|
always @ (posedge clk or posedge rst)
|
|
if (rst)
|
|
qi <= {length{1'b0}};
|
|
else
|
|
if (cke)
|
|
qi <= q_next;
|
|
assign q = qi;
|
|
endmodule
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Versatile counter ////
|
|
//// ////
|
|
//// Description ////
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
|
//// counter ////
|
|
//// ////
|
|
//// To Do: ////
|
|
//// - add LFSR with more taps ////
|
|
//// ////
|
|
//// Author(s): ////
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
|
//// ORSoC AB ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
|
//// ////
|
|
//// This source file may be used and distributed without ////
|
|
//// restriction provided that this copyright statement is not ////
|
|
//// removed from the file and that any derivative work contains ////
|
|
//// the original copyright notice and the associated disclaimer. ////
|
|
//// ////
|
|
//// This source file is free software; you can redistribute it ////
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
|
//// Public License as published by the Free Software Foundation; ////
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
|
//// later version. ////
|
|
//// ////
|
|
//// This source is distributed in the hope that it will be ////
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
|
//// details. ////
|
|
//// ////
|
|
//// You should have received a copy of the GNU Lesser General ////
|
|
//// Public License along with this source; if not, download it ////
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
// binary counter
|
|
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
|
|
parameter length = 4;
|
|
input cke;
|
|
input rew;
|
|
output reg level1;
|
|
input rst;
|
|
input clk;
|
|
parameter clear_value = 0;
|
|
parameter set_value = 1;
|
|
parameter wrap_value = 1;
|
|
parameter level1_value = 15;
|
|
wire clear;
|
|
assign clear = 1'b0;
|
|
reg [length:1] qi;
|
|
wire [length:1] q_next, q_next_fw, q_next_rew;
|
|
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
|
|
assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
|
|
assign q_next = rew ? q_next_rew : q_next_fw;
|
|
always @ (posedge clk or posedge rst)
|
|
if (rst)
|
|
qi <= {length{1'b0}};
|
|
else
|
|
if (cke)
|
|
qi <= q_next;
|
|
always @ (posedge clk or posedge rst)
|
|
if (rst)
|
|
level1 <= 1'b0;
|
|
else
|
|
if (cke)
|
|
if (clear)
|
|
level1 <= 1'b0;
|
|
else if (q_next == level1_value)
|
|
level1 <= 1'b1;
|
|
else if (qi == level1_value & rew)
|
|
level1 <= 1'b0;
|
|
endmodule
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Versatile counter ////
|
|
//// ////
|
|
//// Description ////
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
|
//// counter ////
|
|
//// ////
|
|
//// To Do: ////
|
|
//// - add LFSR with more taps ////
|
|
//// ////
|
|
//// Author(s): ////
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
|
//// ORSoC AB ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
|
//// ////
|
|
//// This source file may be used and distributed without ////
|
|
//// restriction provided that this copyright statement is not ////
|
|
//// removed from the file and that any derivative work contains ////
|
|
//// the original copyright notice and the associated disclaimer. ////
|
|
//// ////
|
|
//// This source file is free software; you can redistribute it ////
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
|
//// Public License as published by the Free Software Foundation; ////
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
|
//// later version. ////
|
|
//// ////
|
|
//// This source is distributed in the hope that it will be ////
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
|
//// details. ////
|
|
//// ////
|
|
//// You should have received a copy of the GNU Lesser General ////
|
|
//// Public License along with this source; if not, download it ////
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
// binary counter
|
|
module vl_cnt_bin_ce_rew_zq_l1 ( cke, rew, zq, level1, rst, clk);
|
|
parameter length = 4;
|
|
input cke;
|
|
input rew;
|
|
output reg zq;
|
|
output reg level1;
|
|
input rst;
|
|
input clk;
|
|
parameter clear_value = 0;
|
|
parameter set_value = 1;
|
|
parameter wrap_value = 1;
|
|
parameter level1_value = 15;
|
|
wire clear;
|
|
assign clear = 1'b0;
|
|
reg [length:1] qi;
|
|
wire [length:1] q_next, q_next_fw, q_next_rew;
|
|
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
|
|
assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
|
|
assign q_next = rew ? q_next_rew : q_next_fw;
|
|
always @ (posedge clk or posedge rst)
|
|
if (rst)
|
|
qi <= {length{1'b0}};
|
|
else
|
|
if (cke)
|
|
qi <= q_next;
|
|
always @ (posedge clk or posedge rst)
|
|
if (rst)
|
|
zq <= 1'b1;
|
|
else
|
|
if (cke)
|
|
zq <= q_next == {length{1'b0}};
|
|
always @ (posedge clk or posedge rst)
|
|
if (rst)
|
|
level1 <= 1'b0;
|
|
else
|
|
if (cke)
|
|
if (clear)
|
|
level1 <= 1'b0;
|
|
else if (q_next == level1_value)
|
|
level1 <= 1'b1;
|
|
else if (qi == level1_value & rew)
|
|
level1 <= 1'b0;
|
|
endmodule
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Versatile counter ////
|
|
//// ////
|
|
//// Description ////
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
|
//// counter ////
|
|
//// ////
|
|
//// To Do: ////
|
|
//// - add LFSR with more taps ////
|
|
//// ////
|
|
//// Author(s): ////
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
|
//// ORSoC AB ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
|
//// ////
|
|
//// This source file may be used and distributed without ////
|
|
//// restriction provided that this copyright statement is not ////
|
|
//// removed from the file and that any derivative work contains ////
|
|
//// the original copyright notice and the associated disclaimer. ////
|
|
//// ////
|
|
//// This source file is free software; you can redistribute it ////
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
|
//// Public License as published by the Free Software Foundation; ////
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
|
//// later version. ////
|
|
//// ////
|
|
//// This source is distributed in the hope that it will be ////
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
|
//// details. ////
|
|
//// ////
|
|
//// You should have received a copy of the GNU Lesser General ////
|
|
//// Public License along with this source; if not, download it ////
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
// binary counter
|
|
module vl_cnt_bin_ce_rew_q_zq_l1 ( cke, rew, q, zq, level1, rst, clk);
|
|
parameter length = 4;
|
|
input cke;
|
|
input rew;
|
|
output [length:1] q;
|
|
output reg zq;
|
|
output reg level1;
|
|
input rst;
|
|
input clk;
|
|
parameter clear_value = 0;
|
|
parameter set_value = 1;
|
|
parameter wrap_value = 1;
|
|
parameter level1_value = 15;
|
|
wire clear;
|
|
assign clear = 1'b0;
|
|
reg [length:1] qi;
|
|
wire [length:1] q_next, q_next_fw, q_next_rew;
|
|
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
|
|
assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
|
|
assign q_next = rew ? q_next_rew : q_next_fw;
|
|
always @ (posedge clk or posedge rst)
|
|
if (rst)
|
|
qi <= {length{1'b0}};
|
|
else
|
|
if (cke)
|
|
qi <= q_next;
|
|
assign q = qi;
|
|
always @ (posedge clk or posedge rst)
|
|
if (rst)
|
|
zq <= 1'b1;
|
|
else
|
|
if (cke)
|
|
zq <= q_next == {length{1'b0}};
|
|
always @ (posedge clk or posedge rst)
|
|
if (rst)
|
|
level1 <= 1'b0;
|
|
else
|
|
if (cke)
|
|
if (clear)
|
|
level1 <= 1'b0;
|
|
else if (q_next == level1_value)
|
|
level1 <= 1'b1;
|
|
else if (qi == level1_value & rew)
|
|
level1 <= 1'b0;
|
|
endmodule
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Versatile counter ////
|
|
//// ////
|
|
//// Description ////
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
|
//// counter ////
|
|
//// ////
|
|
//// To Do: ////
|
|
//// - add LFSR with more taps ////
|
|
//// ////
|
|
//// Author(s): ////
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
|
//// ORSoC AB ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
|
//// ////
|
|
//// This source file may be used and distributed without ////
|
|
//// restriction provided that this copyright statement is not ////
|
|
//// removed from the file and that any derivative work contains ////
|
|
//// the original copyright notice and the associated disclaimer. ////
|
|
//// ////
|
|
//// This source file is free software; you can redistribute it ////
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
|
//// Public License as published by the Free Software Foundation; ////
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
|
//// later version. ////
|
|
//// ////
|
|
//// This source is distributed in the hope that it will be ////
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
|
//// details. ////
|
|
//// ////
|
|
//// You should have received a copy of the GNU Lesser General ////
|
|
//// Public License along with this source; if not, download it ////
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
// LFSR counter
|
|
module vl_cnt_lfsr_zq ( zq, rst, clk);
|
|
parameter length = 4;
|
|
output reg zq;
|
|
input rst;
|
|
input clk;
|
|
parameter clear_value = 0;
|
|
parameter set_value = 1;
|
|
parameter wrap_value = 8;
|
|
parameter level1_value = 15;
|
|
reg [length:1] qi;
|
|
reg lfsr_fb;
|
|
wire [length:1] q_next;
|
|
reg [32:1] polynom;
|
|
integer i;
|
|
always @ (qi)
|
|
begin
|
|
case (length)
|
|
2: polynom = 32'b11; // 0x3
|
|
3: polynom = 32'b110; // 0x6
|
|
4: polynom = 32'b1100; // 0xC
|
|
5: polynom = 32'b10100; // 0x14
|
|
6: polynom = 32'b110000; // 0x30
|
|
7: polynom = 32'b1100000; // 0x60
|
|
8: polynom = 32'b10111000; // 0xb8
|
|
9: polynom = 32'b100010000; // 0x110
|
|
10: polynom = 32'b1001000000; // 0x240
|
|
11: polynom = 32'b10100000000; // 0x500
|
|
12: polynom = 32'b100000101001; // 0x829
|
|
13: polynom = 32'b1000000001100; // 0x100C
|
|
14: polynom = 32'b10000000010101; // 0x2015
|
|
15: polynom = 32'b110000000000000; // 0x6000
|
|
16: polynom = 32'b1101000000001000; // 0xD008
|
|
17: polynom = 32'b10010000000000000; // 0x12000
|
|
18: polynom = 32'b100000010000000000; // 0x20400
|
|
19: polynom = 32'b1000000000000100011; // 0x40023
|
|
20: polynom = 32'b10010000000000000000; // 0x90000
|
|
21: polynom = 32'b101000000000000000000; // 0x140000
|
|
22: polynom = 32'b1100000000000000000000; // 0x300000
|
|
23: polynom = 32'b10000100000000000000000; // 0x420000
|
|
24: polynom = 32'b111000010000000000000000; // 0xE10000
|
|
25: polynom = 32'b1001000000000000000000000; // 0x1200000
|
|
26: polynom = 32'b10000000000000000000100011; // 0x2000023
|
|
27: polynom = 32'b100000000000000000000010011; // 0x4000013
|
|
28: polynom = 32'b1100100000000000000000000000; // 0xC800000
|
|
29: polynom = 32'b10100000000000000000000000000; // 0x14000000
|
|
30: polynom = 32'b100000000000000000000000101001; // 0x20000029
|
|
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
|
|
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
|
|
default: polynom = 32'b0;
|
|
endcase
|
|
lfsr_fb = qi[length];
|
|
for (i=length-1; i>=1; i=i-1) begin
|
|
if (polynom[i])
|
|
lfsr_fb = lfsr_fb ~^ qi[i];
|
|
end
|
|
end
|
|
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
|
|
always @ (posedge clk or posedge rst)
|
|
if (rst)
|
|
qi <= {length{1'b0}};
|
|
else
|
|
qi <= q_next;
|
|
always @ (posedge clk or posedge rst)
|
|
if (rst)
|
|
zq <= 1'b1;
|
|
else
|
|
zq <= q_next == {length{1'b0}};
|
|
endmodule
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Versatile counter ////
|
|
//// ////
|
|
//// Description ////
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
|
//// counter ////
|
|
//// ////
|
|
//// To Do: ////
|
|
//// - add LFSR with more taps ////
|
|
//// ////
|
|
//// Author(s): ////
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
|
//// ORSoC AB ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
|
//// ////
|
|
//// This source file may be used and distributed without ////
|
|
//// restriction provided that this copyright statement is not ////
|
|
//// removed from the file and that any derivative work contains ////
|
|
//// the original copyright notice and the associated disclaimer. ////
|
|
//// ////
|
|
//// This source file is free software; you can redistribute it ////
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
|
//// Public License as published by the Free Software Foundation; ////
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
|
//// later version. ////
|
|
//// ////
|
|
//// This source is distributed in the hope that it will be ////
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
|
//// details. ////
|
|
//// ////
|
|
//// You should have received a copy of the GNU Lesser General ////
|
|
//// Public License along with this source; if not, download it ////
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
// LFSR counter
|
|
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
|
|
parameter length = 4;
|
|
input cke;
|
|
output reg zq;
|
|
input rst;
|
|
input clk;
|
|
parameter clear_value = 0;
|
|
parameter set_value = 1;
|
|
parameter wrap_value = 8;
|
|
parameter level1_value = 15;
|
|
reg [length:1] qi;
|
|
reg lfsr_fb;
|
|
wire [length:1] q_next;
|
|
reg [32:1] polynom;
|
|
integer i;
|
|
always @ (qi)
|
|
begin
|
|
case (length)
|
|
2: polynom = 32'b11; // 0x3
|
|
3: polynom = 32'b110; // 0x6
|
|
4: polynom = 32'b1100; // 0xC
|
|
5: polynom = 32'b10100; // 0x14
|
|
6: polynom = 32'b110000; // 0x30
|
|
7: polynom = 32'b1100000; // 0x60
|
|
8: polynom = 32'b10111000; // 0xb8
|
|
9: polynom = 32'b100010000; // 0x110
|
|
10: polynom = 32'b1001000000; // 0x240
|
|
11: polynom = 32'b10100000000; // 0x500
|
|
12: polynom = 32'b100000101001; // 0x829
|
|
13: polynom = 32'b1000000001100; // 0x100C
|
|
14: polynom = 32'b10000000010101; // 0x2015
|
|
15: polynom = 32'b110000000000000; // 0x6000
|
|
16: polynom = 32'b1101000000001000; // 0xD008
|
|
17: polynom = 32'b10010000000000000; // 0x12000
|
|
18: polynom = 32'b100000010000000000; // 0x20400
|
|
19: polynom = 32'b1000000000000100011; // 0x40023
|
|
20: polynom = 32'b10010000000000000000; // 0x90000
|
|
21: polynom = 32'b101000000000000000000; // 0x140000
|
|
22: polynom = 32'b1100000000000000000000; // 0x300000
|
|
23: polynom = 32'b10000100000000000000000; // 0x420000
|
|
24: polynom = 32'b111000010000000000000000; // 0xE10000
|
|
25: polynom = 32'b1001000000000000000000000; // 0x1200000
|
|
26: polynom = 32'b10000000000000000000100011; // 0x2000023
|
|
27: polynom = 32'b100000000000000000000010011; // 0x4000013
|
|
28: polynom = 32'b1100100000000000000000000000; // 0xC800000
|
|
29: polynom = 32'b10100000000000000000000000000; // 0x14000000
|
|
30: polynom = 32'b100000000000000000000000101001; // 0x20000029
|
|
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
|
|
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
|
|
default: polynom = 32'b0;
|
|
endcase
|
|
lfsr_fb = qi[length];
|
|
for (i=length-1; i>=1; i=i-1) begin
|
|
if (polynom[i])
|
|
lfsr_fb = lfsr_fb ~^ qi[i];
|
|
end
|
|
end
|
|
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
|
|
always @ (posedge clk or posedge rst)
|
|
if (rst)
|
|
qi <= {length{1'b0}};
|
|
else
|
|
if (cke)
|
|
qi <= q_next;
|
|
always @ (posedge clk or posedge rst)
|
|
if (rst)
|
|
zq <= 1'b1;
|
|
else
|
|
if (cke)
|
|
zq <= q_next == {length{1'b0}};
|
|
endmodule
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Versatile counter ////
|
|
//// ////
|
|
//// Description ////
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
|
//// counter ////
|
|
//// ////
|
|
//// To Do: ////
|
|
//// - add LFSR with more taps ////
|
|
//// ////
|
|
//// Author(s): ////
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
|
//// ORSoC AB ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
|
//// ////
|
|
//// This source file may be used and distributed without ////
|
|
//// restriction provided that this copyright statement is not ////
|
|
//// removed from the file and that any derivative work contains ////
|
|
//// the original copyright notice and the associated disclaimer. ////
|
|
//// ////
|
|
//// This source file is free software; you can redistribute it ////
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
|
//// Public License as published by the Free Software Foundation; ////
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
|
//// later version. ////
|
|
//// ////
|
|
//// This source is distributed in the hope that it will be ////
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
|
//// details. ////
|
|
//// ////
|
|
//// You should have received a copy of the GNU Lesser General ////
|
|
//// Public License along with this source; if not, download it ////
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
// LFSR counter
|
|
module vl_cnt_lfsr_ce_q ( cke, q, rst, clk);
|
|
parameter length = 4;
|
parameter length = 4;
|
input cke;
|
input cke;
|
output [length:1] q;
|
output [length:1] q;
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
parameter clear_value = 0;
|
parameter clear_value = 0;
|
parameter set_value = 1;
|
parameter set_value = 1;
|
parameter wrap_value = 8;
|
parameter wrap_value = 0;
|
parameter level1_value = 15;
|
parameter level1_value = 15;
|
reg [length:1] qi;
|
reg [length:1] qi;
|
reg lfsr_fb;
|
|
wire [length:1] q_next;
|
wire [length:1] q_next;
|
reg [32:1] polynom;
|
assign q_next = qi + {{length-1{1'b0}},1'b1};
|
integer i;
|
|
always @ (qi)
|
|
begin
|
|
case (length)
|
|
2: polynom = 32'b11; // 0x3
|
|
3: polynom = 32'b110; // 0x6
|
|
4: polynom = 32'b1100; // 0xC
|
|
5: polynom = 32'b10100; // 0x14
|
|
6: polynom = 32'b110000; // 0x30
|
|
7: polynom = 32'b1100000; // 0x60
|
|
8: polynom = 32'b10111000; // 0xb8
|
|
9: polynom = 32'b100010000; // 0x110
|
|
10: polynom = 32'b1001000000; // 0x240
|
|
11: polynom = 32'b10100000000; // 0x500
|
|
12: polynom = 32'b100000101001; // 0x829
|
|
13: polynom = 32'b1000000001100; // 0x100C
|
|
14: polynom = 32'b10000000010101; // 0x2015
|
|
15: polynom = 32'b110000000000000; // 0x6000
|
|
16: polynom = 32'b1101000000001000; // 0xD008
|
|
17: polynom = 32'b10010000000000000; // 0x12000
|
|
18: polynom = 32'b100000010000000000; // 0x20400
|
|
19: polynom = 32'b1000000000000100011; // 0x40023
|
|
20: polynom = 32'b10010000000000000000; // 0x90000
|
|
21: polynom = 32'b101000000000000000000; // 0x140000
|
|
22: polynom = 32'b1100000000000000000000; // 0x300000
|
|
23: polynom = 32'b10000100000000000000000; // 0x420000
|
|
24: polynom = 32'b111000010000000000000000; // 0xE10000
|
|
25: polynom = 32'b1001000000000000000000000; // 0x1200000
|
|
26: polynom = 32'b10000000000000000000100011; // 0x2000023
|
|
27: polynom = 32'b100000000000000000000010011; // 0x4000013
|
|
28: polynom = 32'b1100100000000000000000000000; // 0xC800000
|
|
29: polynom = 32'b10100000000000000000000000000; // 0x14000000
|
|
30: polynom = 32'b100000000000000000000000101001; // 0x20000029
|
|
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
|
|
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
|
|
default: polynom = 32'b0;
|
|
endcase
|
|
lfsr_fb = qi[length];
|
|
for (i=length-1; i>=1; i=i-1) begin
|
|
if (polynom[i])
|
|
lfsr_fb = lfsr_fb ~^ qi[i];
|
|
end
|
|
end
|
|
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
qi <= {length{1'b0}};
|
qi <= {length{1'b0}};
|
else
|
else
|
if (cke)
|
if (cke)
|
qi <= q_next;
|
qi <= q_next;
|
assign q = qi;
|
assign q = qi;
|
endmodule
|
endmodule
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile counter ////
|
//// Versatile counter ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// counter ////
|
//// counter ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - add LFSR with more taps ////
|
//// - add LFSR with more taps ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
// LFSR counter
|
// binary counter
|
module vl_cnt_lfsr_ce_clear_q ( clear, cke, q, rst, clk);
|
module vl_cnt_bin_ce_rew_zq_l1 (
|
|
cke, rew, zq, level1, rst, clk);
|
parameter length = 4;
|
parameter length = 4;
|
input clear;
|
|
input cke;
|
input cke;
|
output [length:1] q;
|
input rew;
|
|
output reg zq;
|
|
output reg level1;
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
parameter clear_value = 0;
|
parameter clear_value = 0;
|
parameter set_value = 1;
|
parameter set_value = 1;
|
parameter wrap_value = 8;
|
parameter wrap_value = 1;
|
parameter level1_value = 15;
|
parameter level1_value = 15;
|
|
wire clear;
|
|
assign clear = 1'b0;
|
reg [length:1] qi;
|
reg [length:1] qi;
|
reg lfsr_fb;
|
wire [length:1] q_next, q_next_fw, q_next_rew;
|
wire [length:1] q_next;
|
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
|
reg [32:1] polynom;
|
assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
|
integer i;
|
assign q_next = rew ? q_next_rew : q_next_fw;
|
always @ (qi)
|
|
begin
|
|
case (length)
|
|
2: polynom = 32'b11; // 0x3
|
|
3: polynom = 32'b110; // 0x6
|
|
4: polynom = 32'b1100; // 0xC
|
|
5: polynom = 32'b10100; // 0x14
|
|
6: polynom = 32'b110000; // 0x30
|
|
7: polynom = 32'b1100000; // 0x60
|
|
8: polynom = 32'b10111000; // 0xb8
|
|
9: polynom = 32'b100010000; // 0x110
|
|
10: polynom = 32'b1001000000; // 0x240
|
|
11: polynom = 32'b10100000000; // 0x500
|
|
12: polynom = 32'b100000101001; // 0x829
|
|
13: polynom = 32'b1000000001100; // 0x100C
|
|
14: polynom = 32'b10000000010101; // 0x2015
|
|
15: polynom = 32'b110000000000000; // 0x6000
|
|
16: polynom = 32'b1101000000001000; // 0xD008
|
|
17: polynom = 32'b10010000000000000; // 0x12000
|
|
18: polynom = 32'b100000010000000000; // 0x20400
|
|
19: polynom = 32'b1000000000000100011; // 0x40023
|
|
20: polynom = 32'b10010000000000000000; // 0x90000
|
|
21: polynom = 32'b101000000000000000000; // 0x140000
|
|
22: polynom = 32'b1100000000000000000000; // 0x300000
|
|
23: polynom = 32'b10000100000000000000000; // 0x420000
|
|
24: polynom = 32'b111000010000000000000000; // 0xE10000
|
|
25: polynom = 32'b1001000000000000000000000; // 0x1200000
|
|
26: polynom = 32'b10000000000000000000100011; // 0x2000023
|
|
27: polynom = 32'b100000000000000000000010011; // 0x4000013
|
|
28: polynom = 32'b1100100000000000000000000000; // 0xC800000
|
|
29: polynom = 32'b10100000000000000000000000000; // 0x14000000
|
|
30: polynom = 32'b100000000000000000000000101001; // 0x20000029
|
|
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
|
|
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
|
|
default: polynom = 32'b0;
|
|
endcase
|
|
lfsr_fb = qi[length];
|
|
for (i=length-1; i>=1; i=i-1) begin
|
|
if (polynom[i])
|
|
lfsr_fb = lfsr_fb ~^ qi[i];
|
|
end
|
|
end
|
|
assign q_next = clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
qi <= {length{1'b0}};
|
qi <= {length{1'b0}};
|
else
|
else
|
if (cke)
|
if (cke)
|
qi <= q_next;
|
qi <= q_next;
|
assign q = qi;
|
|
endmodule
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Versatile counter ////
|
|
//// ////
|
|
//// Description ////
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
|
//// counter ////
|
|
//// ////
|
|
//// To Do: ////
|
|
//// - add LFSR with more taps ////
|
|
//// ////
|
|
//// Author(s): ////
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
|
//// ORSoC AB ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
|
//// ////
|
|
//// This source file may be used and distributed without ////
|
|
//// restriction provided that this copyright statement is not ////
|
|
//// removed from the file and that any derivative work contains ////
|
|
//// the original copyright notice and the associated disclaimer. ////
|
|
//// ////
|
|
//// This source file is free software; you can redistribute it ////
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
|
//// Public License as published by the Free Software Foundation; ////
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
|
//// later version. ////
|
|
//// ////
|
|
//// This source is distributed in the hope that it will be ////
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
|
//// details. ////
|
|
//// ////
|
|
//// You should have received a copy of the GNU Lesser General ////
|
|
//// Public License along with this source; if not, download it ////
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
// LFSR counter
|
|
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
|
|
parameter length = 4;
|
|
input cke;
|
|
output [length:1] q;
|
|
output reg zq;
|
|
input rst;
|
|
input clk;
|
|
parameter clear_value = 0;
|
|
parameter set_value = 1;
|
|
parameter wrap_value = 8;
|
|
parameter level1_value = 15;
|
|
reg [length:1] qi;
|
|
reg lfsr_fb;
|
|
wire [length:1] q_next;
|
|
reg [32:1] polynom;
|
|
integer i;
|
|
always @ (qi)
|
|
begin
|
|
case (length)
|
|
2: polynom = 32'b11; // 0x3
|
|
3: polynom = 32'b110; // 0x6
|
|
4: polynom = 32'b1100; // 0xC
|
|
5: polynom = 32'b10100; // 0x14
|
|
6: polynom = 32'b110000; // 0x30
|
|
7: polynom = 32'b1100000; // 0x60
|
|
8: polynom = 32'b10111000; // 0xb8
|
|
9: polynom = 32'b100010000; // 0x110
|
|
10: polynom = 32'b1001000000; // 0x240
|
|
11: polynom = 32'b10100000000; // 0x500
|
|
12: polynom = 32'b100000101001; // 0x829
|
|
13: polynom = 32'b1000000001100; // 0x100C
|
|
14: polynom = 32'b10000000010101; // 0x2015
|
|
15: polynom = 32'b110000000000000; // 0x6000
|
|
16: polynom = 32'b1101000000001000; // 0xD008
|
|
17: polynom = 32'b10010000000000000; // 0x12000
|
|
18: polynom = 32'b100000010000000000; // 0x20400
|
|
19: polynom = 32'b1000000000000100011; // 0x40023
|
|
20: polynom = 32'b10010000000000000000; // 0x90000
|
|
21: polynom = 32'b101000000000000000000; // 0x140000
|
|
22: polynom = 32'b1100000000000000000000; // 0x300000
|
|
23: polynom = 32'b10000100000000000000000; // 0x420000
|
|
24: polynom = 32'b111000010000000000000000; // 0xE10000
|
|
25: polynom = 32'b1001000000000000000000000; // 0x1200000
|
|
26: polynom = 32'b10000000000000000000100011; // 0x2000023
|
|
27: polynom = 32'b100000000000000000000010011; // 0x4000013
|
|
28: polynom = 32'b1100100000000000000000000000; // 0xC800000
|
|
29: polynom = 32'b10100000000000000000000000000; // 0x14000000
|
|
30: polynom = 32'b100000000000000000000000101001; // 0x20000029
|
|
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
|
|
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
|
|
default: polynom = 32'b0;
|
|
endcase
|
|
lfsr_fb = qi[length];
|
|
for (i=length-1; i>=1; i=i-1) begin
|
|
if (polynom[i])
|
|
lfsr_fb = lfsr_fb ~^ qi[i];
|
|
end
|
|
end
|
|
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
qi <= {length{1'b0}};
|
zq <= 1'b1;
|
else
|
else
|
if (cke)
|
if (cke)
|
qi <= q_next;
|
zq <= q_next == {length{1'b0}};
|
assign q = qi;
|
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
zq <= 1'b1;
|
level1 <= 1'b0;
|
else
|
else
|
if (cke)
|
if (cke)
|
zq <= q_next == {length{1'b0}};
|
if (clear)
|
|
level1 <= 1'b0;
|
|
else if (q_next == level1_value)
|
|
level1 <= 1'b1;
|
|
else if (qi == level1_value & rew)
|
|
level1 <= 1'b0;
|
endmodule
|
endmodule
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile counter ////
|
//// Versatile counter ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// counter ////
|
//// counter ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - add LFSR with more taps ////
|
//// - add LFSR with more taps ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
// LFSR counter
|
// binary counter
|
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
|
module vl_cnt_bin_ce_rew_q_zq_l1 (
|
|
cke, rew, q, zq, level1, rst, clk);
|
parameter length = 4;
|
parameter length = 4;
|
input cke;
|
input cke;
|
input rew;
|
input rew;
|
|
output [length:1] q;
|
|
output reg zq;
|
output reg level1;
|
output reg level1;
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
parameter clear_value = 0;
|
parameter clear_value = 0;
|
parameter set_value = 1;
|
parameter set_value = 1;
|
parameter wrap_value = 8;
|
parameter wrap_value = 1;
|
parameter level1_value = 15;
|
parameter level1_value = 15;
|
wire clear;
|
wire clear;
|
assign clear = 1'b0;
|
assign clear = 1'b0;
|
reg [length:1] qi;
|
reg [length:1] qi;
|
reg lfsr_fb, lfsr_fb_rew;
|
|
wire [length:1] q_next, q_next_fw, q_next_rew;
|
wire [length:1] q_next, q_next_fw, q_next_rew;
|
reg [32:1] polynom_rew;
|
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
|
integer j;
|
assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
|
reg [32:1] polynom;
|
|
integer i;
|
|
always @ (qi)
|
|
begin
|
|
case (length)
|
|
2: polynom = 32'b11; // 0x3
|
|
3: polynom = 32'b110; // 0x6
|
|
4: polynom = 32'b1100; // 0xC
|
|
5: polynom = 32'b10100; // 0x14
|
|
6: polynom = 32'b110000; // 0x30
|
|
7: polynom = 32'b1100000; // 0x60
|
|
8: polynom = 32'b10111000; // 0xb8
|
|
9: polynom = 32'b100010000; // 0x110
|
|
10: polynom = 32'b1001000000; // 0x240
|
|
11: polynom = 32'b10100000000; // 0x500
|
|
12: polynom = 32'b100000101001; // 0x829
|
|
13: polynom = 32'b1000000001100; // 0x100C
|
|
14: polynom = 32'b10000000010101; // 0x2015
|
|
15: polynom = 32'b110000000000000; // 0x6000
|
|
16: polynom = 32'b1101000000001000; // 0xD008
|
|
17: polynom = 32'b10010000000000000; // 0x12000
|
|
18: polynom = 32'b100000010000000000; // 0x20400
|
|
19: polynom = 32'b1000000000000100011; // 0x40023
|
|
20: polynom = 32'b10010000000000000000; // 0x90000
|
|
21: polynom = 32'b101000000000000000000; // 0x140000
|
|
22: polynom = 32'b1100000000000000000000; // 0x300000
|
|
23: polynom = 32'b10000100000000000000000; // 0x420000
|
|
24: polynom = 32'b111000010000000000000000; // 0xE10000
|
|
25: polynom = 32'b1001000000000000000000000; // 0x1200000
|
|
26: polynom = 32'b10000000000000000000100011; // 0x2000023
|
|
27: polynom = 32'b100000000000000000000010011; // 0x4000013
|
|
28: polynom = 32'b1100100000000000000000000000; // 0xC800000
|
|
29: polynom = 32'b10100000000000000000000000000; // 0x14000000
|
|
30: polynom = 32'b100000000000000000000000101001; // 0x20000029
|
|
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
|
|
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
|
|
default: polynom = 32'b0;
|
|
endcase
|
|
lfsr_fb = qi[length];
|
|
for (i=length-1; i>=1; i=i-1) begin
|
|
if (polynom[i])
|
|
lfsr_fb = lfsr_fb ~^ qi[i];
|
|
end
|
|
end
|
|
assign q_next_fw = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
|
|
always @ (qi)
|
|
begin
|
|
case (length)
|
|
2: polynom_rew = 32'b11;
|
|
3: polynom_rew = 32'b110;
|
|
4: polynom_rew = 32'b1100;
|
|
5: polynom_rew = 32'b10100;
|
|
6: polynom_rew = 32'b110000;
|
|
7: polynom_rew = 32'b1100000;
|
|
8: polynom_rew = 32'b10111000;
|
|
9: polynom_rew = 32'b100010000;
|
|
10: polynom_rew = 32'b1001000000;
|
|
11: polynom_rew = 32'b10100000000;
|
|
12: polynom_rew = 32'b100000101001;
|
|
13: polynom_rew = 32'b1000000001100;
|
|
14: polynom_rew = 32'b10000000010101;
|
|
15: polynom_rew = 32'b110000000000000;
|
|
16: polynom_rew = 32'b1101000000001000;
|
|
17: polynom_rew = 32'b10010000000000000;
|
|
18: polynom_rew = 32'b100000010000000000;
|
|
19: polynom_rew = 32'b1000000000000100011;
|
|
20: polynom_rew = 32'b10000010000000000000;
|
|
21: polynom_rew = 32'b101000000000000000000;
|
|
22: polynom_rew = 32'b1100000000000000000000;
|
|
23: polynom_rew = 32'b10000100000000000000000;
|
|
24: polynom_rew = 32'b111000010000000000000000;
|
|
25: polynom_rew = 32'b1001000000000000000000000;
|
|
26: polynom_rew = 32'b10000000000000000000100011;
|
|
27: polynom_rew = 32'b100000000000000000000010011;
|
|
28: polynom_rew = 32'b1100100000000000000000000000;
|
|
29: polynom_rew = 32'b10100000000000000000000000000;
|
|
30: polynom_rew = 32'b100000000000000000000000101001;
|
|
31: polynom_rew = 32'b1001000000000000000000000000000;
|
|
32: polynom_rew = 32'b10000000001000000000000000000011;
|
|
default: polynom_rew = 32'b0;
|
|
endcase
|
|
// rotate left
|
|
polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
|
|
lfsr_fb_rew = qi[length];
|
|
for (i=length-1; i>=1; i=i-1) begin
|
|
if (polynom_rew[i])
|
|
lfsr_fb_rew = lfsr_fb_rew ~^ qi[i];
|
|
end
|
|
end
|
|
assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
|
|
assign q_next = rew ? q_next_rew : q_next_fw;
|
assign q_next = rew ? q_next_rew : q_next_fw;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
qi <= {length{1'b0}};
|
qi <= {length{1'b0}};
|
else
|
else
|
if (cke)
|
if (cke)
|
qi <= q_next;
|
qi <= q_next;
|
|
assign q = qi;
|
|
always @ (posedge clk or posedge rst)
|
|
if (rst)
|
|
zq <= 1'b1;
|
|
else
|
|
if (cke)
|
|
zq <= q_next == {length{1'b0}};
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
level1 <= 1'b0;
|
level1 <= 1'b0;
|
else
|
else
|
if (cke)
|
if (cke)
|
if (clear)
|
if (clear)
|
level1 <= 1'b0;
|
level1 <= 1'b0;
|
else if (q_next == level1_value)
|
else if (q_next == level1_value)
|
level1 <= 1'b1;
|
level1 <= 1'b1;
|
else if (qi == level1_value & rew)
|
else if (qi == level1_value & rew)
|
level1 <= 1'b0;
|
level1 <= 1'b0;
|
endmodule
|
endmodule
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile counter ////
|
//// Versatile counter ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
//// counter ////
|
//// counter ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - add LFSR with more taps ////
|
//// - add LFSR with more taps ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
// GRAY counter
|
// GRAY counter
|
module vl_cnt_gray ( q, rst, clk);
|
module vl_cnt_gray_ce_bin (
|
parameter length = 4;
|
cke, q, q_bin, rst, clk);
|
output reg [length:1] q;
|
|
input rst;
|
|
input clk;
|
|
parameter clear_value = 0;
|
|
parameter set_value = 1;
|
|
parameter wrap_value = 8;
|
|
parameter level1_value = 15;
|
|
reg [length:1] qi;
|
|
wire [length:1] q_next;
|
|
assign q_next = qi + {{length-1{1'b0}},1'b1};
|
|
always @ (posedge clk or posedge rst)
|
|
if (rst)
|
|
qi <= {length{1'b0}};
|
|
else
|
|
qi <= q_next;
|
|
always @ (posedge clk or posedge rst)
|
|
if (rst)
|
|
q <= {length{1'b0}};
|
|
else
|
|
q <= (q_next>>1) ^ q_next;
|
|
endmodule
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Versatile counter ////
|
|
//// ////
|
|
//// Description ////
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
|
//// counter ////
|
|
//// ////
|
|
//// To Do: ////
|
|
//// - add LFSR with more taps ////
|
|
//// ////
|
|
//// Author(s): ////
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
|
//// ORSoC AB ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
|
//// ////
|
|
//// This source file may be used and distributed without ////
|
|
//// restriction provided that this copyright statement is not ////
|
|
//// removed from the file and that any derivative work contains ////
|
|
//// the original copyright notice and the associated disclaimer. ////
|
|
//// ////
|
|
//// This source file is free software; you can redistribute it ////
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
|
//// Public License as published by the Free Software Foundation; ////
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
|
//// later version. ////
|
|
//// ////
|
|
//// This source is distributed in the hope that it will be ////
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
|
//// details. ////
|
|
//// ////
|
|
//// You should have received a copy of the GNU Lesser General ////
|
|
//// Public License along with this source; if not, download it ////
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
// GRAY counter
|
|
module vl_cnt_gray_ce ( cke, q, rst, clk);
|
|
parameter length = 4;
|
|
input cke;
|
|
output reg [length:1] q;
|
|
input rst;
|
|
input clk;
|
|
parameter clear_value = 0;
|
|
parameter set_value = 1;
|
|
parameter wrap_value = 8;
|
|
parameter level1_value = 15;
|
|
reg [length:1] qi;
|
|
wire [length:1] q_next;
|
|
assign q_next = qi + {{length-1{1'b0}},1'b1};
|
|
always @ (posedge clk or posedge rst)
|
|
if (rst)
|
|
qi <= {length{1'b0}};
|
|
else
|
|
if (cke)
|
|
qi <= q_next;
|
|
always @ (posedge clk or posedge rst)
|
|
if (rst)
|
|
q <= {length{1'b0}};
|
|
else
|
|
if (cke)
|
|
q <= (q_next>>1) ^ q_next;
|
|
endmodule
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Versatile counter ////
|
|
//// ////
|
|
//// Description ////
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
|
//// counter ////
|
|
//// ////
|
|
//// To Do: ////
|
|
//// - add LFSR with more taps ////
|
|
//// ////
|
|
//// Author(s): ////
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
|
//// ORSoC AB ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
//// ////
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
|
//// ////
|
|
//// This source file may be used and distributed without ////
|
|
//// restriction provided that this copyright statement is not ////
|
|
//// removed from the file and that any derivative work contains ////
|
|
//// the original copyright notice and the associated disclaimer. ////
|
|
//// ////
|
|
//// This source file is free software; you can redistribute it ////
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
|
//// Public License as published by the Free Software Foundation; ////
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
|
//// later version. ////
|
|
//// ////
|
|
//// This source is distributed in the hope that it will be ////
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
|
//// details. ////
|
|
//// ////
|
|
//// You should have received a copy of the GNU Lesser General ////
|
|
//// Public License along with this source; if not, download it ////
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
|
//// ////
|
|
//////////////////////////////////////////////////////////////////////
|
|
// GRAY counter
|
|
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
|
|
parameter length = 4;
|
parameter length = 4;
|
input cke;
|
input cke;
|
output reg [length:1] q;
|
output reg [length:1] q;
|
output [length:1] q_bin;
|
output [length:1] q_bin;
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
parameter clear_value = 0;
|
parameter clear_value = 0;
|
parameter set_value = 1;
|
parameter set_value = 1;
|
parameter wrap_value = 8;
|
parameter wrap_value = 8;
|
parameter level1_value = 15;
|
parameter level1_value = 15;
|
reg [length:1] qi;
|
reg [length:1] qi;
|
wire [length:1] q_next;
|
wire [length:1] q_next;
|
assign q_next = qi + {{length-1{1'b0}},1'b1};
|
assign q_next = qi + {{length-1{1'b0}},1'b1};
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
qi <= {length{1'b0}};
|
qi <= {length{1'b0}};
|
else
|
else
|
if (cke)
|
if (cke)
|
qi <= q_next;
|
qi <= q_next;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= {length{1'b0}};
|
q <= {length{1'b0}};
|
else
|
else
|
if (cke)
|
if (cke)
|
q <= (q_next>>1) ^ q_next;
|
q <= (q_next>>1) ^ q_next;
|
assign q_bin = qi;
|
assign q_bin = qi;
|
endmodule
|
endmodule
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile library, counters ////
|
//// Versatile library, counters ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// counters ////
|
//// counters ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - add more counters ////
|
//// - add more counters ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
module vl_cnt_shreg_wrap ( q, rst, clk);
|
module vl_cnt_shreg_wrap ( q, rst, clk);
|
parameter length = 4;
|
parameter length = 4;
|
output reg [0:length-1] q;
|
output reg [0:length-1] q;
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= {1'b1,{length-1{1'b0}}};
|
q <= {1'b1,{length-1{1'b0}}};
|
else
|
else
|
q <= {q[length-1],q[0:length-2]};
|
q <= {q[length-1],q[0:length-2]};
|
endmodule
|
endmodule
|
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
|
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
|
parameter length = 4;
|
parameter length = 4;
|
input cke;
|
input cke;
|
output reg [0:length-1] q;
|
output reg [0:length-1] q;
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= {1'b1,{length-1{1'b0}}};
|
q <= {1'b1,{length-1{1'b0}}};
|
else
|
else
|
if (cke)
|
if (cke)
|
q <= {q[length-1],q[0:length-2]};
|
q <= {q[length-1],q[0:length-2]};
|
endmodule
|
endmodule
|
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
|
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
|
parameter length = 4;
|
parameter length = 4;
|
input cke, clear;
|
input cke, clear;
|
output reg [0:length-1] q;
|
output reg [0:length-1] q;
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= {1'b1,{length-1{1'b0}}};
|
q <= {1'b1,{length-1{1'b0}}};
|
else
|
else
|
if (cke)
|
if (cke)
|
if (clear)
|
if (clear)
|
q <= {1'b1,{length-1{1'b0}}};
|
q <= {1'b1,{length-1{1'b0}}};
|
else
|
else
|
q <= q >> 1;
|
q <= q >> 1;
|
endmodule
|
endmodule
|
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
|
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
|
parameter length = 4;
|
parameter length = 4;
|
input cke, clear;
|
input cke, clear;
|
output reg [0:length-1] q;
|
output reg [0:length-1] q;
|
input rst;
|
input rst;
|
input clk;
|
input clk;
|
always @ (posedge clk or posedge rst)
|
always @ (posedge clk or posedge rst)
|
if (rst)
|
if (rst)
|
q <= {1'b1,{length-1{1'b0}}};
|
q <= {1'b1,{length-1{1'b0}}};
|
else
|
else
|
if (cke)
|
if (cke)
|
if (clear)
|
if (clear)
|
q <= {1'b1,{length-1{1'b0}}};
|
q <= {1'b1,{length-1{1'b0}}};
|
else
|
else
|
q <= {q[length-1],q[0:length-2]};
|
q <= {q[length-1],q[0:length-2]};
|
endmodule
|
endmodule
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile library, memories ////
|
//// Versatile library, memories ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// memories ////
|
//// memories ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - add more memory types ////
|
//// - add more memory types ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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/// ROM
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/// ROM
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module vl_rom_init ( adr, q, clk);
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module vl_rom_init ( adr, q, clk);
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parameter data_width = 32;
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parameter data_width = 32;
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parameter addr_width = 8;
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parameter addr_width = 8;
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input [(addr_width-1):0] adr;
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input [(addr_width-1):0] adr;
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output reg [(data_width-1):0] q;
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output reg [(data_width-1):0] q;
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input clk;
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input clk;
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reg [data_width-1:0] rom [(1<<addr_width)-1:0];
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reg [data_width-1:0] rom [(1<<addr_width)-1:0];
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parameter memory_file = "vl_rom.vmem";
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parameter memory_file = "vl_rom.vmem";
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initial
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initial
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begin
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begin
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$readmemh(memory_file, rom);
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$readmemh(memory_file, rom);
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end
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end
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always @ (posedge clk)
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always @ (posedge clk)
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q <= rom[adr];
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q <= rom[adr];
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endmodule
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endmodule
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/*
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/*
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module vl_rom ( adr, q, clk);
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module vl_rom ( adr, q, clk);
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parameter data_width = 32;
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parameter data_width = 32;
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parameter addr_width = 4;
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parameter addr_width = 4;
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parameter [0:1>>addr_width-1] data [data_width-1:0] = {
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parameter [0:1>>addr_width-1] data [data_width-1:0] = {
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{32'h18000000},
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{32'h18000000},
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{32'hA8200000},
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{32'hA8200000},
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{32'hA8200000},
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{32'hA8200000},
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{32'hA8200000},
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{32'hA8200000},
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{32'h44003000},
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{32'h44003000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000}};
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{32'h15000000}};
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input [addr_width-1:0] adr;
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input [addr_width-1:0] adr;
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output reg [data_width-1:0] q;
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output reg [data_width-1:0] q;
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input clk;
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input clk;
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always @ (posedge clk)
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always @ (posedge clk)
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q <= data[adr];
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q <= data[adr];
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endmodule
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endmodule
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*/
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*/
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// Single port RAM
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// Single port RAM
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module vl_ram ( d, adr, we, q, clk);
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module vl_ram ( d, adr, we, q, clk);
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parameter data_width = 32;
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parameter data_width = 32;
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parameter addr_width = 8;
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parameter addr_width = 8;
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input [(data_width-1):0] d;
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input [(data_width-1):0] d;
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input [(addr_width-1):0] adr;
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input [(addr_width-1):0] adr;
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input we;
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input we;
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output reg [(data_width-1):0] q;
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output reg [(data_width-1):0] q;
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input clk;
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input clk;
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reg [data_width-1:0] ram [(1<<addr_width)-1:0];
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reg [data_width-1:0] ram [(1<<addr_width)-1:0];
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parameter init = 0;
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parameter init = 0;
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parameter memory_file = "vl_ram.vmem";
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parameter memory_file = "vl_ram.vmem";
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generate if (init) begin : init_mem
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generate if (init) begin : init_mem
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initial
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initial
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begin
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begin
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$readmemh(memory_file, ram);
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$readmemh(memory_file, ram);
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end
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end
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end
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end
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endgenerate
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endgenerate
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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if (we)
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if (we)
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ram[adr] <= d;
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ram[adr] <= d;
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q <= ram[adr];
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q <= ram[adr];
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end
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end
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endmodule
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endmodule
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module vl_ram_be ( d, adr, be, we, q, clk);
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module vl_ram_be ( d, adr, be, we, q, clk);
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parameter data_width = 32;
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parameter data_width = 32;
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parameter addr_width = 8;
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parameter addr_width = 8;
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input [(data_width-1):0] d;
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input [(data_width-1):0] d;
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input [(addr_width-1):0] adr;
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input [(addr_width-1):0] adr;
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input [(addr_width/4)-1:0] be;
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input [(addr_width/4)-1:0] be;
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input we;
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input we;
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output reg [(data_width-1):0] q;
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output reg [(data_width-1):0] q;
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input clk;
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input clk;
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reg [data_width-1:0] ram [(1<<addr_width)-1:0];
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reg [data_width-1:0] ram [(1<<addr_width)-1:0];
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parameter init = 0;
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parameter init = 0;
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parameter memory_file = "vl_ram.vmem";
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parameter memory_file = "vl_ram.vmem";
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generate if (init) begin : init_mem
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generate if (init) begin : init_mem
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initial
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initial
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begin
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begin
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$readmemh(memory_file, ram);
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$readmemh(memory_file, ram);
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end
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end
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end
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end
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endgenerate
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endgenerate
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genvar i;
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genvar i;
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generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
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generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
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always @ (posedge clk)
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always @ (posedge clk)
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if (we & be[i])
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if (we & be[i])
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ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
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ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
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end
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end
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endgenerate
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endgenerate
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always @ (posedge clk)
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always @ (posedge clk)
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q <= ram[adr];
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q <= ram[adr];
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endmodule
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endmodule
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// Dual port RAM
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// Dual port RAM
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// ACTEL FPGA should not use logic to handle rw collision
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// ACTEL FPGA should not use logic to handle rw collision
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module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
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module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
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parameter data_width = 32;
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parameter data_width = 32;
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parameter addr_width = 8;
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parameter addr_width = 8;
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input [(data_width-1):0] d_a;
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input [(data_width-1):0] d_a;
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input [(addr_width-1):0] adr_a;
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input [(addr_width-1):0] adr_a;
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input [(addr_width-1):0] adr_b;
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input [(addr_width-1):0] adr_b;
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input we_a;
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input we_a;
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output [(data_width-1):0] q_b;
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output [(data_width-1):0] q_b;
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input clk_a, clk_b;
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input clk_a, clk_b;
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reg [(addr_width-1):0] adr_b_reg;
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reg [(addr_width-1):0] adr_b_reg;
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reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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parameter init = 0;
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parameter init = 0;
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parameter memory_file = "vl_ram.vmem";
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parameter memory_file = "vl_ram.vmem";
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generate if (init) begin : init_mem
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generate if (init) begin : init_mem
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initial
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initial
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begin
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begin
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$readmemh(memory_file, ram);
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$readmemh(memory_file, ram);
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end
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end
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end
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end
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endgenerate
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endgenerate
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always @ (posedge clk_a)
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always @ (posedge clk_a)
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if (we_a)
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if (we_a)
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ram[adr_a] <= d_a;
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ram[adr_a] <= d_a;
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always @ (posedge clk_b)
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always @ (posedge clk_b)
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adr_b_reg <= adr_b;
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adr_b_reg <= adr_b;
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assign q_b = ram[adr_b_reg];
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assign q_b = ram[adr_b_reg];
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endmodule
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endmodule
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module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
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module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
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parameter data_width = 32;
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parameter data_width = 32;
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parameter addr_width = 8;
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parameter addr_width = 8;
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input [(data_width-1):0] d_a;
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input [(data_width-1):0] d_a;
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input [(addr_width-1):0] adr_a;
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input [(addr_width-1):0] adr_a;
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input [(addr_width-1):0] adr_b;
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input [(addr_width-1):0] adr_b;
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input we_a;
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input we_a;
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output [(data_width-1):0] q_b;
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output [(data_width-1):0] q_b;
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output reg [(data_width-1):0] q_a;
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output reg [(data_width-1):0] q_a;
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input clk_a, clk_b;
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input clk_a, clk_b;
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reg [(data_width-1):0] q_b;
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reg [(data_width-1):0] q_b;
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reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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parameter init = 0;
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parameter init = 0;
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parameter memory_file = "vl_ram.vmem";
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parameter memory_file = "vl_ram.vmem";
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generate if (init) begin : init_mem
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generate if (init) begin : init_mem
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initial
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initial
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begin
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begin
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$readmemh(memory_file, ram);
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$readmemh(memory_file, ram);
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end
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end
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end
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end
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endgenerate
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endgenerate
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always @ (posedge clk_a)
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always @ (posedge clk_a)
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begin
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begin
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q_a <= ram[adr_a];
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q_a <= ram[adr_a];
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if (we_a)
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if (we_a)
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ram[adr_a] <= d_a;
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ram[adr_a] <= d_a;
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end
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end
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always @ (posedge clk_b)
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always @ (posedge clk_b)
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q_b <= ram[adr_b];
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q_b <= ram[adr_b];
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endmodule
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endmodule
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module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
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module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
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parameter data_width = 32;
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parameter data_width = 32;
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parameter addr_width = 8;
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parameter addr_width = 8;
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input [(data_width-1):0] d_a;
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input [(data_width-1):0] d_a;
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input [(addr_width-1):0] adr_a;
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input [(addr_width-1):0] adr_a;
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input [(addr_width-1):0] adr_b;
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input [(addr_width-1):0] adr_b;
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input we_a;
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input we_a;
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output [(data_width-1):0] q_b;
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output [(data_width-1):0] q_b;
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input [(data_width-1):0] d_b;
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input [(data_width-1):0] d_b;
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output reg [(data_width-1):0] q_a;
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output reg [(data_width-1):0] q_a;
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input we_b;
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input we_b;
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input clk_a, clk_b;
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input clk_a, clk_b;
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reg [(data_width-1):0] q_b;
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reg [(data_width-1):0] q_b;
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reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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parameter init = 0;
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parameter init = 0;
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parameter memory_file = "vl_ram.vmem";
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parameter memory_file = "vl_ram.vmem";
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generate if (init) begin : init_mem
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generate if (init) begin : init_mem
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initial
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initial
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begin
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begin
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$readmemh(memory_file, ram);
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$readmemh(memory_file, ram);
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end
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end
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end
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end
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endgenerate
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endgenerate
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always @ (posedge clk_a)
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always @ (posedge clk_a)
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begin
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begin
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q_a <= ram[adr_a];
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q_a <= ram[adr_a];
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if (we_a)
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if (we_a)
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ram[adr_a] <= d_a;
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ram[adr_a] <= d_a;
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end
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end
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always @ (posedge clk_b)
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always @ (posedge clk_b)
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begin
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begin
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q_b <= ram[adr_b];
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q_b <= ram[adr_b];
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if (we_b)
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if (we_b)
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ram[adr_b] <= d_b;
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ram[adr_b] <= d_b;
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end
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end
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endmodule
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endmodule
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// Content addresable memory, CAM
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// Content addresable memory, CAM
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// FIFO
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// FIFO
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module vl_fifo_1r1w_fill_level_sync (
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module vl_fifo_1r1w_fill_level_sync (
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d, wr, fifo_full,
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d, wr, fifo_full,
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q, rd, fifo_empty,
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q, rd, fifo_empty,
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fill_level,
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fill_level,
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clk, rst
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clk, rst
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);
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);
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parameter data_width = 18;
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parameter data_width = 18;
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parameter addr_width = 4;
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parameter addr_width = 4;
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// write side
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// write side
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input [data_width-1:0] d;
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input [data_width-1:0] d;
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input wr;
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input wr;
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output fifo_full;
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output fifo_full;
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// read side
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// read side
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output [data_width-1:0] q;
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output [data_width-1:0] q;
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input rd;
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input rd;
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output fifo_empty;
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output fifo_empty;
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// common
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// common
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output [addr_width:0] fill_level;
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output [addr_width:0] fill_level;
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input rst, clk;
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input rst, clk;
|
wire [addr_width:1] wadr, radr;
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wire [addr_width:1] wadr, radr;
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vl_cnt_bin_ce
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vl_cnt_bin_ce
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# ( .length(addr_width))
|
# ( .length(addr_width))
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fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
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fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
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vl_cnt_bin_ce
|
vl_cnt_bin_ce
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# (.length(addr_width))
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# (.length(addr_width))
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fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
|
fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
|
vl_dpram_1r1w
|
vl_dpram_1r1w
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# (.data_width(data_width), .addr_width(addr_width))
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# (.data_width(data_width), .addr_width(addr_width))
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dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
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dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
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vl_cnt_bin_ce_rew_q_zq_l1
|
vl_cnt_bin_ce_rew_q_zq_l1
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# (.length(addr_width+1), .level1_value(1<<addr_width))
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# (.length(addr_width+1), .level1_value(1<<addr_width))
|
fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
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fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
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endmodule
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endmodule
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// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
|
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
|
// RAM is supposed to be larger than the two FIFOs
|
// RAM is supposed to be larger than the two FIFOs
|
// LFSR counters used adr pointers
|
// LFSR counters used adr pointers
|
module vl_fifo_2r2w_sync_simplex (
|
module vl_fifo_2r2w_sync_simplex (
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// a side
|
// a side
|
a_d, a_wr, a_fifo_full,
|
a_d, a_wr, a_fifo_full,
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a_q, a_rd, a_fifo_empty,
|
a_q, a_rd, a_fifo_empty,
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a_fill_level,
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a_fill_level,
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// b side
|
// b side
|
b_d, b_wr, b_fifo_full,
|
b_d, b_wr, b_fifo_full,
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b_q, b_rd, b_fifo_empty,
|
b_q, b_rd, b_fifo_empty,
|
b_fill_level,
|
b_fill_level,
|
// common
|
// common
|
clk, rst
|
clk, rst
|
);
|
);
|
parameter data_width = 8;
|
parameter data_width = 8;
|
parameter addr_width = 5;
|
parameter addr_width = 5;
|
parameter fifo_full_level = (1<<addr_width)-1;
|
parameter fifo_full_level = (1<<addr_width)-1;
|
// a side
|
// a side
|
input [data_width-1:0] a_d;
|
input [data_width-1:0] a_d;
|
input a_wr;
|
input a_wr;
|
output a_fifo_full;
|
output a_fifo_full;
|
output [data_width-1:0] a_q;
|
output [data_width-1:0] a_q;
|
input a_rd;
|
input a_rd;
|
output a_fifo_empty;
|
output a_fifo_empty;
|
output [addr_width-1:0] a_fill_level;
|
output [addr_width-1:0] a_fill_level;
|
// b side
|
// b side
|
input [data_width-1:0] b_d;
|
input [data_width-1:0] b_d;
|
input b_wr;
|
input b_wr;
|
output b_fifo_full;
|
output b_fifo_full;
|
output [data_width-1:0] b_q;
|
output [data_width-1:0] b_q;
|
input b_rd;
|
input b_rd;
|
output b_fifo_empty;
|
output b_fifo_empty;
|
output [addr_width-1:0] b_fill_level;
|
output [addr_width-1:0] b_fill_level;
|
input clk;
|
input clk;
|
input rst;
|
input rst;
|
// adr_gen
|
// adr_gen
|
wire [addr_width:1] a_wadr, a_radr;
|
wire [addr_width:1] a_wadr, a_radr;
|
wire [addr_width:1] b_wadr, b_radr;
|
wire [addr_width:1] b_wadr, b_radr;
|
// dpram
|
// dpram
|
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
|
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
|
vl_cnt_lfsr_ce
|
vl_cnt_lfsr_ce
|
# ( .length(addr_width))
|
# ( .length(addr_width))
|
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
|
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
|
vl_cnt_lfsr_ce
|
vl_cnt_lfsr_ce
|
# (.length(addr_width))
|
# (.length(addr_width))
|
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
|
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
|
vl_cnt_lfsr_ce
|
vl_cnt_lfsr_ce
|
# ( .length(addr_width))
|
# ( .length(addr_width))
|
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
|
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
|
vl_cnt_lfsr_ce
|
vl_cnt_lfsr_ce
|
# (.length(addr_width))
|
# (.length(addr_width))
|
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
|
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
|
// mux read or write adr to DPRAM
|
// mux read or write adr to DPRAM
|
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
|
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
|
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
|
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
|
vl_dpram_2r2w
|
vl_dpram_2r2w
|
# (.data_width(data_width), .addr_width(addr_width+1))
|
# (.data_width(data_width), .addr_width(addr_width+1))
|
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
|
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
|
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
|
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
|
vl_cnt_bin_ce_rew_zq_l1
|
vl_cnt_bin_ce_rew_zq_l1
|
# (.length(addr_width), .level1_value(fifo_full_level))
|
# (.length(addr_width), .level1_value(fifo_full_level))
|
a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
|
a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
|
vl_cnt_bin_ce_rew_zq_l1
|
vl_cnt_bin_ce_rew_zq_l1
|
# (.length(addr_width), .level1_value(fifo_full_level))
|
# (.length(addr_width), .level1_value(fifo_full_level))
|
b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
|
b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
|
endmodule
|
endmodule
|
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
|
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
|
parameter addr_width = 4;
|
parameter addr_width = 4;
|
parameter N = addr_width-1;
|
parameter N = addr_width-1;
|
parameter Q1 = 2'b00;
|
parameter Q1 = 2'b00;
|
parameter Q2 = 2'b01;
|
parameter Q2 = 2'b01;
|
parameter Q3 = 2'b11;
|
parameter Q3 = 2'b11;
|
parameter Q4 = 2'b10;
|
parameter Q4 = 2'b10;
|
parameter going_empty = 1'b0;
|
parameter going_empty = 1'b0;
|
parameter going_full = 1'b1;
|
parameter going_full = 1'b1;
|
input [N:0] wptr, rptr;
|
input [N:0] wptr, rptr;
|
output fifo_empty;
|
output fifo_empty;
|
output fifo_full;
|
output fifo_full;
|
input wclk, rclk, rst;
|
input wclk, rclk, rst;
|
wire direction;
|
wire direction;
|
reg direction_set, direction_clr;
|
reg direction_set, direction_clr;
|
wire async_empty, async_full;
|
wire async_empty, async_full;
|
wire fifo_full2;
|
wire fifo_full2;
|
wire fifo_empty2;
|
wire fifo_empty2;
|
// direction_set
|
// direction_set
|
always @ (wptr[N:N-1] or rptr[N:N-1])
|
always @ (wptr[N:N-1] or rptr[N:N-1])
|
case ({wptr[N:N-1],rptr[N:N-1]})
|
case ({wptr[N:N-1],rptr[N:N-1]})
|
{Q1,Q2} : direction_set <= 1'b1;
|
{Q1,Q2} : direction_set <= 1'b1;
|
{Q2,Q3} : direction_set <= 1'b1;
|
{Q2,Q3} : direction_set <= 1'b1;
|
{Q3,Q4} : direction_set <= 1'b1;
|
{Q3,Q4} : direction_set <= 1'b1;
|
{Q4,Q1} : direction_set <= 1'b1;
|
{Q4,Q1} : direction_set <= 1'b1;
|
default : direction_set <= 1'b0;
|
default : direction_set <= 1'b0;
|
endcase
|
endcase
|
// direction_clear
|
// direction_clear
|
always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
|
always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
|
if (rst)
|
if (rst)
|
direction_clr <= 1'b1;
|
direction_clr <= 1'b1;
|
else
|
else
|
case ({wptr[N:N-1],rptr[N:N-1]})
|
case ({wptr[N:N-1],rptr[N:N-1]})
|
{Q2,Q1} : direction_clr <= 1'b1;
|
{Q2,Q1} : direction_clr <= 1'b1;
|
{Q3,Q2} : direction_clr <= 1'b1;
|
{Q3,Q2} : direction_clr <= 1'b1;
|
{Q4,Q3} : direction_clr <= 1'b1;
|
{Q4,Q3} : direction_clr <= 1'b1;
|
{Q1,Q4} : direction_clr <= 1'b1;
|
{Q1,Q4} : direction_clr <= 1'b1;
|
default : direction_clr <= 1'b0;
|
default : direction_clr <= 1'b0;
|
endcase
|
endcase
|
vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
|
vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
|
assign async_empty = (wptr == rptr) && (direction==going_empty);
|
assign async_empty = (wptr == rptr) && (direction==going_empty);
|
assign async_full = (wptr == rptr) && (direction==going_full);
|
assign async_full = (wptr == rptr) && (direction==going_full);
|
vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
|
vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
|
vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
|
vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
|
/*
|
/*
|
always @ (posedge wclk or posedge rst or posedge async_full)
|
always @ (posedge wclk or posedge rst or posedge async_full)
|
if (rst)
|
if (rst)
|
{fifo_full, fifo_full2} <= 2'b00;
|
{fifo_full, fifo_full2} <= 2'b00;
|
else if (async_full)
|
else if (async_full)
|
{fifo_full, fifo_full2} <= 2'b11;
|
{fifo_full, fifo_full2} <= 2'b11;
|
else
|
else
|
{fifo_full, fifo_full2} <= {fifo_full2, async_full};
|
{fifo_full, fifo_full2} <= {fifo_full2, async_full};
|
*/
|
*/
|
/* always @ (posedge rclk or posedge async_empty)
|
/* always @ (posedge rclk or posedge async_empty)
|
if (async_empty)
|
if (async_empty)
|
{fifo_empty, fifo_empty2} <= 2'b11;
|
{fifo_empty, fifo_empty2} <= 2'b11;
|
else
|
else
|
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
|
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
|
vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
|
vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
|
vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty));
|
vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty));
|
endmodule // async_compb
|
endmodule // async_compb
|
module vl_fifo_1r1w_async (
|
module vl_fifo_1r1w_async (
|
d, wr, fifo_full, wr_clk, wr_rst,
|
d, wr, fifo_full, wr_clk, wr_rst,
|
q, rd, fifo_empty, rd_clk, rd_rst
|
q, rd, fifo_empty, rd_clk, rd_rst
|
);
|
);
|
parameter data_width = 18;
|
parameter data_width = 18;
|
parameter addr_width = 4;
|
parameter addr_width = 4;
|
// write side
|
// write side
|
input [data_width-1:0] d;
|
input [data_width-1:0] d;
|
input wr;
|
input wr;
|
output fifo_full;
|
output fifo_full;
|
input wr_clk;
|
input wr_clk;
|
input wr_rst;
|
input wr_rst;
|
// read side
|
// read side
|
output [data_width-1:0] q;
|
output [data_width-1:0] q;
|
input rd;
|
input rd;
|
output fifo_empty;
|
output fifo_empty;
|
input rd_clk;
|
input rd_clk;
|
input rd_rst;
|
input rd_rst;
|
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
|
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
|
vl_cnt_gray_ce_bin
|
vl_cnt_gray_ce_bin
|
# ( .length(addr_width))
|
# ( .length(addr_width))
|
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
|
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
|
vl_cnt_gray_ce_bin
|
vl_cnt_gray_ce_bin
|
# (.length(addr_width))
|
# (.length(addr_width))
|
fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
|
fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
|
vl_dpram_1r1w
|
vl_dpram_1r1w
|
# (.data_width(data_width), .addr_width(addr_width))
|
# (.data_width(data_width), .addr_width(addr_width))
|
dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
|
dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
|
vl_fifo_cmp_async
|
vl_fifo_cmp_async
|
# (.addr_width(addr_width))
|
# (.addr_width(addr_width))
|
cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
|
cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
|
endmodule
|
endmodule
|
module vl_fifo_2r2w_async (
|
module vl_fifo_2r2w_async (
|
// a side
|
// a side
|
a_d, a_wr, a_fifo_full,
|
a_d, a_wr, a_fifo_full,
|
a_q, a_rd, a_fifo_empty,
|
a_q, a_rd, a_fifo_empty,
|
a_clk, a_rst,
|
a_clk, a_rst,
|
// b side
|
// b side
|
b_d, b_wr, b_fifo_full,
|
b_d, b_wr, b_fifo_full,
|
b_q, b_rd, b_fifo_empty,
|
b_q, b_rd, b_fifo_empty,
|
b_clk, b_rst
|
b_clk, b_rst
|
);
|
);
|
parameter data_width = 18;
|
parameter data_width = 18;
|
parameter addr_width = 4;
|
parameter addr_width = 4;
|
// a side
|
// a side
|
input [data_width-1:0] a_d;
|
input [data_width-1:0] a_d;
|
input a_wr;
|
input a_wr;
|
output a_fifo_full;
|
output a_fifo_full;
|
output [data_width-1:0] a_q;
|
output [data_width-1:0] a_q;
|
input a_rd;
|
input a_rd;
|
output a_fifo_empty;
|
output a_fifo_empty;
|
input a_clk;
|
input a_clk;
|
input a_rst;
|
input a_rst;
|
// b side
|
// b side
|
input [data_width-1:0] b_d;
|
input [data_width-1:0] b_d;
|
input b_wr;
|
input b_wr;
|
output b_fifo_full;
|
output b_fifo_full;
|
output [data_width-1:0] b_q;
|
output [data_width-1:0] b_q;
|
input b_rd;
|
input b_rd;
|
output b_fifo_empty;
|
output b_fifo_empty;
|
input b_clk;
|
input b_clk;
|
input b_rst;
|
input b_rst;
|
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
|
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
|
vl_fifo_1r1w_async_a (
|
vl_fifo_1r1w_async_a (
|
.d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
|
.d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
|
.q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
|
.q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
|
);
|
);
|
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
|
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
|
vl_fifo_1r1w_async_b (
|
vl_fifo_1r1w_async_b (
|
.d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
|
.d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
|
.q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
|
.q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
|
);
|
);
|
endmodule
|
endmodule
|
module vl_fifo_2r2w_async_simplex (
|
module vl_fifo_2r2w_async_simplex (
|
// a side
|
// a side
|
a_d, a_wr, a_fifo_full,
|
a_d, a_wr, a_fifo_full,
|
a_q, a_rd, a_fifo_empty,
|
a_q, a_rd, a_fifo_empty,
|
a_clk, a_rst,
|
a_clk, a_rst,
|
// b side
|
// b side
|
b_d, b_wr, b_fifo_full,
|
b_d, b_wr, b_fifo_full,
|
b_q, b_rd, b_fifo_empty,
|
b_q, b_rd, b_fifo_empty,
|
b_clk, b_rst
|
b_clk, b_rst
|
);
|
);
|
parameter data_width = 18;
|
parameter data_width = 18;
|
parameter addr_width = 4;
|
parameter addr_width = 4;
|
// a side
|
// a side
|
input [data_width-1:0] a_d;
|
input [data_width-1:0] a_d;
|
input a_wr;
|
input a_wr;
|
output a_fifo_full;
|
output a_fifo_full;
|
output [data_width-1:0] a_q;
|
output [data_width-1:0] a_q;
|
input a_rd;
|
input a_rd;
|
output a_fifo_empty;
|
output a_fifo_empty;
|
input a_clk;
|
input a_clk;
|
input a_rst;
|
input a_rst;
|
// b side
|
// b side
|
input [data_width-1:0] b_d;
|
input [data_width-1:0] b_d;
|
input b_wr;
|
input b_wr;
|
output b_fifo_full;
|
output b_fifo_full;
|
output [data_width-1:0] b_q;
|
output [data_width-1:0] b_q;
|
input b_rd;
|
input b_rd;
|
output b_fifo_empty;
|
output b_fifo_empty;
|
input b_clk;
|
input b_clk;
|
input b_rst;
|
input b_rst;
|
// adr_gen
|
// adr_gen
|
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
|
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
|
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
|
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
|
// dpram
|
// dpram
|
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
|
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
|
vl_cnt_gray_ce_bin
|
vl_cnt_gray_ce_bin
|
# ( .length(addr_width))
|
# ( .length(addr_width))
|
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
|
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
|
vl_cnt_gray_ce_bin
|
vl_cnt_gray_ce_bin
|
# (.length(addr_width))
|
# (.length(addr_width))
|
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
|
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
|
vl_cnt_gray_ce_bin
|
vl_cnt_gray_ce_bin
|
# ( .length(addr_width))
|
# ( .length(addr_width))
|
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
|
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
|
vl_cnt_gray_ce_bin
|
vl_cnt_gray_ce_bin
|
# (.length(addr_width))
|
# (.length(addr_width))
|
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
|
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
|
// mux read or write adr to DPRAM
|
// mux read or write adr to DPRAM
|
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
|
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
|
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
|
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
|
vl_dpram_2r2w
|
vl_dpram_2r2w
|
# (.data_width(data_width), .addr_width(addr_width+1))
|
# (.data_width(data_width), .addr_width(addr_width+1))
|
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
|
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
|
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
|
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
|
vl_fifo_cmp_async
|
vl_fifo_cmp_async
|
# (.addr_width(addr_width))
|
# (.addr_width(addr_width))
|
cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
|
cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
|
vl_fifo_cmp_async
|
vl_fifo_cmp_async
|
# (.addr_width(addr_width))
|
# (.addr_width(addr_width))
|
cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
|
cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
|
endmodule
|
endmodule
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile library, wishbone stuff ////
|
//// Versatile library, wishbone stuff ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Wishbone compliant modules ////
|
//// Wishbone compliant modules ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - ////
|
//// - ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
// async wb3 - wb3 bridge
|
// async wb3 - wb3 bridge
|
`timescale 1ns/1ns
|
`timescale 1ns/1ns
|
module vl_wb3wb3_bridge (
|
module vl_wb3wb3_bridge (
|
// wishbone slave side
|
// wishbone slave side
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
|
// wishbone master side
|
// wishbone master side
|
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
|
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
|
input [31:0] wbs_dat_i;
|
input [31:0] wbs_dat_i;
|
input [31:2] wbs_adr_i;
|
input [31:2] wbs_adr_i;
|
input [3:0] wbs_sel_i;
|
input [3:0] wbs_sel_i;
|
input [1:0] wbs_bte_i;
|
input [1:0] wbs_bte_i;
|
input [2:0] wbs_cti_i;
|
input [2:0] wbs_cti_i;
|
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
|
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
|
output [31:0] wbs_dat_o;
|
output [31:0] wbs_dat_o;
|
output wbs_ack_o;
|
output wbs_ack_o;
|
input wbs_clk, wbs_rst;
|
input wbs_clk, wbs_rst;
|
output [31:0] wbm_dat_o;
|
output [31:0] wbm_dat_o;
|
output reg [31:2] wbm_adr_o;
|
output reg [31:2] wbm_adr_o;
|
output [3:0] wbm_sel_o;
|
output [3:0] wbm_sel_o;
|
output reg [1:0] wbm_bte_o;
|
output reg [1:0] wbm_bte_o;
|
output reg [2:0] wbm_cti_o;
|
output reg [2:0] wbm_cti_o;
|
output reg wbm_we_o;
|
output reg wbm_we_o;
|
output wbm_cyc_o;
|
output wbm_cyc_o;
|
output wbm_stb_o;
|
output wbm_stb_o;
|
input [31:0] wbm_dat_i;
|
input [31:0] wbm_dat_i;
|
input wbm_ack_i;
|
input wbm_ack_i;
|
input wbm_clk, wbm_rst;
|
input wbm_clk, wbm_rst;
|
parameter addr_width = 4;
|
parameter addr_width = 4;
|
// bte
|
// bte
|
parameter linear = 2'b00;
|
parameter linear = 2'b00;
|
parameter wrap4 = 2'b01;
|
parameter wrap4 = 2'b01;
|
parameter wrap8 = 2'b10;
|
parameter wrap8 = 2'b10;
|
parameter wrap16 = 2'b11;
|
parameter wrap16 = 2'b11;
|
// cti
|
// cti
|
parameter classic = 3'b000;
|
parameter classic = 3'b000;
|
parameter incburst = 3'b010;
|
parameter incburst = 3'b010;
|
parameter endofburst = 3'b111;
|
parameter endofburst = 3'b111;
|
parameter wbs_adr = 1'b0;
|
parameter wbs_adr = 1'b0;
|
parameter wbs_data = 1'b1;
|
parameter wbs_data = 1'b1;
|
parameter wbm_adr0 = 2'b00;
|
parameter wbm_adr0 = 2'b00;
|
parameter wbm_adr1 = 2'b01;
|
parameter wbm_adr1 = 2'b01;
|
parameter wbm_data = 2'b10;
|
parameter wbm_data = 2'b10;
|
parameter wbm_data_wait = 2'b11;
|
parameter wbm_data_wait = 2'b11;
|
reg [1:0] wbs_bte_reg;
|
reg [1:0] wbs_bte_reg;
|
reg wbs;
|
reg wbs;
|
wire wbs_eoc_alert, wbm_eoc_alert;
|
wire wbs_eoc_alert, wbm_eoc_alert;
|
reg wbs_eoc, wbm_eoc;
|
reg wbs_eoc, wbm_eoc;
|
reg [1:0] wbm;
|
reg [1:0] wbm;
|
wire [1:16] wbs_count, wbm_count;
|
wire [1:16] wbs_count, wbm_count;
|
wire [35:0] a_d, a_q, b_d, b_q;
|
wire [35:0] a_d, a_q, b_d, b_q;
|
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
|
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
|
reg a_rd_reg;
|
reg a_rd_reg;
|
wire b_rd_adr, b_rd_data;
|
wire b_rd_adr, b_rd_data;
|
wire b_rd_data_reg;
|
wire b_rd_data_reg;
|
wire [35:0] temp;
|
wire [35:0] temp;
|
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
|
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
if (wbs_rst)
|
if (wbs_rst)
|
wbs_eoc <= 1'b0;
|
wbs_eoc <= 1'b0;
|
else
|
else
|
if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
|
if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
|
wbs_eoc <= wbs_bte_i==linear;
|
wbs_eoc <= wbs_bte_i==linear;
|
else if (wbs_eoc_alert & (a_rd | a_wr))
|
else if (wbs_eoc_alert & (a_rd | a_wr))
|
wbs_eoc <= 1'b1;
|
wbs_eoc <= 1'b1;
|
vl_cnt_shreg_ce_clear # ( .length(16))
|
vl_cnt_shreg_ce_clear # ( .length(16))
|
cnt0 (
|
cnt0 (
|
.cke(wbs_ack_o),
|
.cke(wbs_ack_o),
|
.clear(wbs_eoc),
|
.clear(wbs_eoc),
|
.q(wbs_count),
|
.q(wbs_count),
|
.rst(wbs_rst),
|
.rst(wbs_rst),
|
.clk(wbs_clk));
|
.clk(wbs_clk));
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
if (wbs_rst)
|
if (wbs_rst)
|
wbs <= wbs_adr;
|
wbs <= wbs_adr;
|
else
|
else
|
if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
|
if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
|
wbs <= wbs_data;
|
wbs <= wbs_data;
|
else if (wbs_eoc & wbs_ack_o)
|
else if (wbs_eoc & wbs_ack_o)
|
wbs <= wbs_adr;
|
wbs <= wbs_adr;
|
// wbs FIFO
|
// wbs FIFO
|
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
|
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
|
assign a_wr = (wbs==wbs_adr) ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
|
assign a_wr = (wbs==wbs_adr) ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
|
(wbs==wbs_data) ? wbs_we_i & wbs_stb_i & !a_fifo_full :
|
(wbs==wbs_data) ? wbs_we_i & wbs_stb_i & !a_fifo_full :
|
1'b0;
|
1'b0;
|
assign a_rd = !a_fifo_empty;
|
assign a_rd = !a_fifo_empty;
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
if (wbs_rst)
|
if (wbs_rst)
|
a_rd_reg <= 1'b0;
|
a_rd_reg <= 1'b0;
|
else
|
else
|
a_rd_reg <= a_rd;
|
a_rd_reg <= a_rd;
|
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
|
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
|
assign wbs_dat_o = a_q[35:4];
|
assign wbs_dat_o = a_q[35:4];
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
if (wbs_rst)
|
if (wbs_rst)
|
wbs_bte_reg <= 2'b00;
|
wbs_bte_reg <= 2'b00;
|
else
|
else
|
wbs_bte_reg <= wbs_bte_i;
|
wbs_bte_reg <= wbs_bte_i;
|
// wbm FIFO
|
// wbm FIFO
|
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
|
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
if (wbm_rst)
|
if (wbm_rst)
|
wbm_eoc <= 1'b0;
|
wbm_eoc <= 1'b0;
|
else
|
else
|
if (wbm==wbm_adr0 & !b_fifo_empty)
|
if (wbm==wbm_adr0 & !b_fifo_empty)
|
wbm_eoc <= b_q[4:3] == linear;
|
wbm_eoc <= b_q[4:3] == linear;
|
else if (wbm_eoc_alert & wbm_ack_i)
|
else if (wbm_eoc_alert & wbm_ack_i)
|
wbm_eoc <= 1'b1;
|
wbm_eoc <= 1'b1;
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
if (wbm_rst)
|
if (wbm_rst)
|
wbm <= wbm_adr0;
|
wbm <= wbm_adr0;
|
else
|
else
|
/*
|
/*
|
if ((wbm==wbm_adr0 & !b_fifo_empty) |
|
if ((wbm==wbm_adr0 & !b_fifo_empty) |
|
(wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
|
(wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
|
(wbm==wbm_adr1 & !wbm_we_o) |
|
(wbm==wbm_adr1 & !wbm_we_o) |
|
(wbm==wbm_data & wbm_ack_i & wbm_eoc))
|
(wbm==wbm_data & wbm_ack_i & wbm_eoc))
|
wbm <= {wbm[0],!(wbm[1] ^ wbm[0])}; // count sequence 00,01,10
|
wbm <= {wbm[0],!(wbm[1] ^ wbm[0])}; // count sequence 00,01,10
|
*/
|
*/
|
case (wbm)
|
case (wbm)
|
wbm_adr0:
|
wbm_adr0:
|
if (!b_fifo_empty)
|
if (!b_fifo_empty)
|
wbm <= wbm_adr1;
|
wbm <= wbm_adr1;
|
wbm_adr1:
|
wbm_adr1:
|
if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
|
if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
|
wbm <= wbm_data;
|
wbm <= wbm_data;
|
wbm_data:
|
wbm_data:
|
if (wbm_ack_i & wbm_eoc)
|
if (wbm_ack_i & wbm_eoc)
|
wbm <= wbm_adr0;
|
wbm <= wbm_adr0;
|
else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
|
else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
|
wbm <= wbm_data_wait;
|
wbm <= wbm_data_wait;
|
wbm_data_wait:
|
wbm_data_wait:
|
if (!b_fifo_empty)
|
if (!b_fifo_empty)
|
wbm <= wbm_data;
|
wbm <= wbm_data;
|
endcase
|
endcase
|
assign b_d = {wbm_dat_i,4'b1111};
|
assign b_d = {wbm_dat_i,4'b1111};
|
assign b_wr = !wbm_we_o & wbm_ack_i;
|
assign b_wr = !wbm_we_o & wbm_ack_i;
|
assign b_rd_adr = (wbm==wbm_adr0 & !b_fifo_empty);
|
assign b_rd_adr = (wbm==wbm_adr0 & !b_fifo_empty);
|
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
|
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
|
(wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
|
(wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
|
(wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
|
(wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
|
1'b0;
|
1'b0;
|
assign b_rd = b_rd_adr | b_rd_data;
|
assign b_rd = b_rd_adr | b_rd_data;
|
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
|
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
|
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
|
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
|
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
|
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
|
vl_cnt_shreg_ce_clear # ( .length(16))
|
vl_cnt_shreg_ce_clear # ( .length(16))
|
cnt1 (
|
cnt1 (
|
.cke(wbm_ack_i),
|
.cke(wbm_ack_i),
|
.clear(wbm_eoc),
|
.clear(wbm_eoc),
|
.q(wbm_count),
|
.q(wbm_count),
|
.rst(wbm_rst),
|
.rst(wbm_rst),
|
.clk(wbm_clk));
|
.clk(wbm_clk));
|
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
|
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
|
assign wbm_stb_o = (wbm==wbm_data);
|
assign wbm_stb_o = (wbm==wbm_data);
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
if (wbm_rst)
|
if (wbm_rst)
|
{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
|
{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
|
else begin
|
else begin
|
if (wbm==wbm_adr0 & !b_fifo_empty)
|
if (wbm==wbm_adr0 & !b_fifo_empty)
|
{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
|
{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
|
else if (wbm_eoc_alert & wbm_ack_i)
|
else if (wbm_eoc_alert & wbm_ack_i)
|
wbm_cti_o <= endofburst;
|
wbm_cti_o <= endofburst;
|
end
|
end
|
//async_fifo_dw_simplex_top
|
//async_fifo_dw_simplex_top
|
vl_fifo_2r2w_async_simplex
|
vl_fifo_2r2w_async_simplex
|
# ( .data_width(36), .addr_width(addr_width))
|
# ( .data_width(36), .addr_width(addr_width))
|
fifo (
|
fifo (
|
// a side
|
// a side
|
.a_d(a_d),
|
.a_d(a_d),
|
.a_wr(a_wr),
|
.a_wr(a_wr),
|
.a_fifo_full(a_fifo_full),
|
.a_fifo_full(a_fifo_full),
|
.a_q(a_q),
|
.a_q(a_q),
|
.a_rd(a_rd),
|
.a_rd(a_rd),
|
.a_fifo_empty(a_fifo_empty),
|
.a_fifo_empty(a_fifo_empty),
|
.a_clk(wbs_clk),
|
.a_clk(wbs_clk),
|
.a_rst(wbs_rst),
|
.a_rst(wbs_rst),
|
// b side
|
// b side
|
.b_d(b_d),
|
.b_d(b_d),
|
.b_wr(b_wr),
|
.b_wr(b_wr),
|
.b_fifo_full(b_fifo_full),
|
.b_fifo_full(b_fifo_full),
|
.b_q(b_q),
|
.b_q(b_q),
|
.b_rd(b_rd),
|
.b_rd(b_rd),
|
.b_fifo_empty(b_fifo_empty),
|
.b_fifo_empty(b_fifo_empty),
|
.b_clk(wbm_clk),
|
.b_clk(wbm_clk),
|
.b_rst(wbm_rst)
|
.b_rst(wbm_rst)
|
);
|
);
|
endmodule
|
endmodule
|
module vl_wb3_arbiter_type1 (
|
module vl_wb3_arbiter_type1 (
|
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
|
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
|
wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
|
wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
|
wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
|
wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
|
wb_clk, wb_rst
|
wb_clk, wb_rst
|
);
|
);
|
parameter nr_of_ports = 3;
|
parameter nr_of_ports = 3;
|
parameter adr_size = 26;
|
parameter adr_size = 26;
|
parameter adr_lo = 2;
|
parameter adr_lo = 2;
|
parameter dat_size = 32;
|
parameter dat_size = 32;
|
parameter sel_size = dat_size/8;
|
parameter sel_size = dat_size/8;
|
localparam aw = (adr_size - adr_lo) * nr_of_ports;
|
localparam aw = (adr_size - adr_lo) * nr_of_ports;
|
localparam dw = dat_size * nr_of_ports;
|
localparam dw = dat_size * nr_of_ports;
|
localparam sw = sel_size * nr_of_ports;
|
localparam sw = sel_size * nr_of_ports;
|
localparam cw = 3 * nr_of_ports;
|
localparam cw = 3 * nr_of_ports;
|
localparam bw = 2 * nr_of_ports;
|
localparam bw = 2 * nr_of_ports;
|
input [dw-1:0] wbm_dat_o;
|
input [dw-1:0] wbm_dat_o;
|
input [aw-1:0] wbm_adr_o;
|
input [aw-1:0] wbm_adr_o;
|
input [sw-1:0] wbm_sel_o;
|
input [sw-1:0] wbm_sel_o;
|
input [cw-1:0] wbm_cti_o;
|
input [cw-1:0] wbm_cti_o;
|
input [bw-1:0] wbm_bte_o;
|
input [bw-1:0] wbm_bte_o;
|
input [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
|
input [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
|
output [dw-1:0] wbm_dat_i;
|
output [dw-1:0] wbm_dat_i;
|
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
|
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
|
output [dat_size-1:0] wbs_dat_i;
|
output [dat_size-1:0] wbs_dat_i;
|
output [adr_size-1:adr_lo] wbs_adr_i;
|
output [adr_size-1:adr_lo] wbs_adr_i;
|
output [sel_size-1:0] wbs_sel_i;
|
output [sel_size-1:0] wbs_sel_i;
|
output [2:0] wbs_cti_i;
|
output [2:0] wbs_cti_i;
|
output [1:0] wbs_bte_i;
|
output [1:0] wbs_bte_i;
|
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
|
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
|
input [dat_size-1:0] wbs_dat_o;
|
input [dat_size-1:0] wbs_dat_o;
|
input wbs_ack_o, wbs_err_o, wbs_rty_o;
|
input wbs_ack_o, wbs_err_o, wbs_rty_o;
|
input wb_clk, wb_rst;
|
input wb_clk, wb_rst;
|
wire [nr_of_ports-1:0] select;
|
wire [nr_of_ports-1:0] select;
|
wire [nr_of_ports-1:0] state;
|
wire [nr_of_ports-1:0] state;
|
wire [nr_of_ports-1:0] eoc; // end-of-cycle
|
wire [nr_of_ports-1:0] eoc; // end-of-cycle
|
wire [nr_of_ports-1:0] sel;
|
wire [nr_of_ports-1:0] sel;
|
wire idle;
|
wire idle;
|
genvar i;
|
genvar i;
|
assign idle = !(|state);
|
assign idle = !(|state);
|
generate
|
generate
|
if (nr_of_ports == 2) begin
|
if (nr_of_ports == 2) begin
|
wire [2:0] wbm1_cti_o, wbm0_cti_o;
|
wire [2:0] wbm1_cti_o, wbm0_cti_o;
|
assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : 2'b00;
|
assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : 2'b00;
|
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
end
|
end
|
endgenerate
|
endgenerate
|
generate
|
generate
|
if (nr_of_ports == 3) begin
|
if (nr_of_ports == 3) begin
|
wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
|
wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
|
assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : 3'b000;
|
assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : 3'b000;
|
assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
|
assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
|
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
end
|
end
|
endgenerate
|
endgenerate
|
generate
|
generate
|
for (i=0;i<nr_of_ports;i=i+1) begin
|
for (i=0;i<nr_of_ports;i=i+1) begin
|
vl_spr sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
|
vl_spr sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
|
end
|
end
|
endgenerate
|
endgenerate
|
assign sel = select | state;
|
assign sel = select | state;
|
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
|
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
|
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
|
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
|
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
|
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
|
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
|
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
|
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
|
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
|
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
|
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
|
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
|
vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
|
assign wbs_cyc_i = |sel;
|
assign wbs_cyc_i = |sel;
|
assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
|
assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
|
assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
|
assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
|
assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
|
assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
|
assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
|
assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
|
endmodule
|
endmodule
|
// WB ROM
|
// WB ROM
|
module vl_wb_boot_rom (
|
module vl_wb_boot_rom (
|
wb_adr_i, wb_stb_i, wb_cyc_i,
|
wb_adr_i, wb_stb_i, wb_cyc_i,
|
wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
|
wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
|
parameter adr_hi = 31;
|
parameter adr_hi = 31;
|
parameter adr_lo = 28;
|
parameter adr_lo = 28;
|
parameter adr_sel = 4'hf;
|
parameter adr_sel = 4'hf;
|
parameter addr_width = 5;
|
parameter addr_width = 5;
|
/*
|
/*
|
`ifndef BOOT_ROM
|
`ifndef BOOT_ROM
|
`define BOOT_ROM "boot_rom.v"
|
`define BOOT_ROM "boot_rom.v"
|
`endif
|
`endif
|
*/
|
*/
|
input [adr_hi:2] wb_adr_i;
|
input [adr_hi:2] wb_adr_i;
|
input wb_stb_i;
|
input wb_stb_i;
|
input wb_cyc_i;
|
input wb_cyc_i;
|
output [31:0] wb_dat_o;
|
output [31:0] wb_dat_o;
|
output wb_ack_o;
|
output wb_ack_o;
|
output hit_o;
|
output hit_o;
|
input wb_clk;
|
input wb_clk;
|
input wb_rst;
|
input wb_rst;
|
wire hit;
|
wire hit;
|
reg [31:0] wb_dat;
|
reg [31:0] wb_dat;
|
reg wb_ack;
|
reg wb_ack;
|
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
|
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
|
always @ (posedge wb_clk or posedge wb_rst)
|
always @ (posedge wb_clk or posedge wb_rst)
|
if (wb_rst)
|
if (wb_rst)
|
wb_dat <= 32'h15000000;
|
wb_dat <= 32'h15000000;
|
else
|
else
|
case (wb_adr_i[addr_width-1:2])
|
case (wb_adr_i[addr_width-1:2])
|
`ifdef BOOT_ROM
|
`ifdef BOOT_ROM
|
`include `BOOT_ROM
|
`include `BOOT_ROM
|
`endif
|
`endif
|
/*
|
/*
|
// Zero r0 and jump to 0x00000100
|
// Zero r0 and jump to 0x00000100
|
0 : wb_dat <= 32'h18000000;
|
0 : wb_dat <= 32'h18000000;
|
1 : wb_dat <= 32'hA8200000;
|
1 : wb_dat <= 32'hA8200000;
|
2 : wb_dat <= 32'hA8C00100;
|
2 : wb_dat <= 32'hA8C00100;
|
3 : wb_dat <= 32'h44003000;
|
3 : wb_dat <= 32'h44003000;
|
4 : wb_dat <= 32'h15000000;
|
4 : wb_dat <= 32'h15000000;
|
*/
|
*/
|
default:
|
default:
|
wb_dat <= 32'h00000000;
|
wb_dat <= 32'h00000000;
|
endcase // case (wb_adr_i)
|
endcase // case (wb_adr_i)
|
always @ (posedge wb_clk or posedge wb_rst)
|
always @ (posedge wb_clk or posedge wb_rst)
|
if (wb_rst)
|
if (wb_rst)
|
wb_ack <= 1'b0;
|
wb_ack <= 1'b0;
|
else
|
else
|
wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
|
wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
|
assign hit_o = hit;
|
assign hit_o = hit;
|
assign wb_dat_o = wb_dat & {32{wb_ack}};
|
assign wb_dat_o = wb_dat & {32{wb_ack}};
|
assign wb_ack_o = wb_ack;
|
assign wb_ack_o = wb_ack;
|
endmodule
|
endmodule
|
module vl_wb_dpram (
|
module vl_wb_dpram (
|
// wishbone slave side a
|
// wishbone slave side a
|
wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
|
wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
|
wbsa_clk, wbsa_rst,
|
wbsa_clk, wbsa_rst,
|
// wishbone slave side a
|
// wishbone slave side a
|
wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
|
wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
|
wbsb_clk, wbsb_rst);
|
wbsb_clk, wbsb_rst);
|
parameter data_width = 32;
|
parameter data_width = 32;
|
parameter addr_width = 8;
|
parameter addr_width = 8;
|
parameter dat_o_mask_a = 1;
|
parameter dat_o_mask_a = 1;
|
parameter dat_o_mask_b = 1;
|
parameter dat_o_mask_b = 1;
|
input [31:0] wbsa_dat_i;
|
input [31:0] wbsa_dat_i;
|
input [addr_width-1:2] wbsa_adr_i;
|
input [addr_width-1:2] wbsa_adr_i;
|
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
|
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
|
output [31:0] wbsa_dat_o;
|
output [31:0] wbsa_dat_o;
|
output wbsa_ack_o;
|
output wbsa_ack_o;
|
input wbsa_clk, wbsa_rst;
|
input wbsa_clk, wbsa_rst;
|
input [31:0] wbsb_dat_i;
|
input [31:0] wbsb_dat_i;
|
input [addr_width-1:2] wbsb_adr_i;
|
input [addr_width-1:2] wbsb_adr_i;
|
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
|
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
|
output [31:0] wbsb_dat_o;
|
output [31:0] wbsb_dat_o;
|
output wbsb_ack_o;
|
output wbsb_ack_o;
|
input wbsb_clk, wbsb_rst;
|
input wbsb_clk, wbsb_rst;
|
wire wbsa_dat_tmp, wbsb_dat_tmp;
|
wire wbsa_dat_tmp, wbsb_dat_tmp;
|
vl_dpram_2r2w # (
|
vl_dpram_2r2w # (
|
.data_width(data_width), .addr_width(addr_width) )
|
.data_width(data_width), .addr_width(addr_width) )
|
dpram0(
|
dpram0(
|
.d_a(wbsa_dat_i),
|
.d_a(wbsa_dat_i),
|
.q_a(wbsa_dat_tmp),
|
.q_a(wbsa_dat_tmp),
|
.adr_a(wbsa_adr_i),
|
.adr_a(wbsa_adr_i),
|
.we_a(wbsa_we_i),
|
.we_a(wbsa_we_i),
|
.clk_a(wbsa_clk),
|
.clk_a(wbsa_clk),
|
.d_b(wbsb_dat_i),
|
.d_b(wbsb_dat_i),
|
.q_b(wbsb_dat_tmp),
|
.q_b(wbsb_dat_tmp),
|
.adr_b(wbsb_adr_i),
|
.adr_b(wbsb_adr_i),
|
.we_b(wbsb_we_i),
|
.we_b(wbsb_we_i),
|
.clk_b(wbsb_clk) );
|
.clk_b(wbsb_clk) );
|
generate if (dat_o_mask_a==1)
|
generate if (dat_o_mask_a==1)
|
assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
|
assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
|
endgenerate
|
endgenerate
|
generate if (dat_o_mask_a==0)
|
generate if (dat_o_mask_a==0)
|
assign wbsa_dat_o = wbsa_dat_tmp;
|
assign wbsa_dat_o = wbsa_dat_tmp;
|
endgenerate
|
endgenerate
|
generate if (dat_o_mask_b==1)
|
generate if (dat_o_mask_b==1)
|
assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
|
assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
|
endgenerate
|
endgenerate
|
generate if (dat_o_mask_b==0)
|
generate if (dat_o_mask_b==0)
|
assign wbsb_dat_o = wbsb_dat_tmp;
|
assign wbsb_dat_o = wbsb_dat_tmp;
|
endgenerate
|
endgenerate
|
vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
|
vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
|
vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
|
vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
|
endmodule
|
endmodule
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Arithmetic functions ////
|
//// Arithmetic functions ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Arithmetic functions for ALU and DSP ////
|
//// Arithmetic functions for ALU and DSP ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - ////
|
//// - ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// - Michael Unneback, unneback@opencores.org ////
|
//// ORSoC AB ////
|
//// ORSoC AB ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// Public License as published by the Free Software Foundation; ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
|
//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
// signed multiplication
|
// signed multiplication
|
module vl_mults (a,b,p);
|
module vl_mults (a,b,p);
|
parameter operand_a_width = 18;
|
parameter operand_a_width = 18;
|
parameter operand_b_width = 18;
|
parameter operand_b_width = 18;
|
parameter result_hi = 35;
|
parameter result_hi = 35;
|
parameter result_lo = 0;
|
parameter result_lo = 0;
|
input [operand_a_width-1:0] a;
|
input [operand_a_width-1:0] a;
|
input [operand_b_width-1:0] b;
|
input [operand_b_width-1:0] b;
|
output [result_hi:result_lo] p;
|
output [result_hi:result_lo] p;
|
wire signed [operand_a_width-1:0] ai;
|
wire signed [operand_a_width-1:0] ai;
|
wire signed [operand_b_width-1:0] bi;
|
wire signed [operand_b_width-1:0] bi;
|
wire signed [operand_a_width+operand_b_width-1:0] result;
|
wire signed [operand_a_width+operand_b_width-1:0] result;
|
assign ai = a;
|
assign ai = a;
|
assign bi = b;
|
assign bi = b;
|
assign result = ai * bi;
|
assign result = ai * bi;
|
assign p = result[result_hi:result_lo];
|
assign p = result[result_hi:result_lo];
|
endmodule
|
endmodule
|
module vl_mults18x18 (a,b,p);
|
module vl_mults18x18 (a,b,p);
|
input [17:0] a,b;
|
input [17:0] a,b;
|
output [35:0] p;
|
output [35:0] p;
|
vl_mult
|
vl_mult
|
# (.operand_a_width(18), .operand_b_width(18))
|
# (.operand_a_width(18), .operand_b_width(18))
|
mult0 (.a(a), .b(b), .p(p));
|
mult0 (.a(a), .b(b), .p(p));
|
endmodule
|
endmodule
|
// unsigned multiplication
|
// unsigned multiplication
|
module vl_mult (a,b,p);
|
module vl_mult (a,b,p);
|
parameter operand_a_width = 18;
|
parameter operand_a_width = 18;
|
parameter operand_b_width = 18;
|
parameter operand_b_width = 18;
|
parameter result_hi = 35;
|
parameter result_hi = 35;
|
parameter result_lo = 0;
|
parameter result_lo = 0;
|
input [operand_a_width-1:0] a;
|
input [operand_a_width-1:0] a;
|
input [operand_b_width-1:0] b;
|
input [operand_b_width-1:0] b;
|
output [result_hi:result_hi] p;
|
output [result_hi:result_hi] p;
|
wire [operand_a_width+operand_b_width-1:0] result;
|
wire [operand_a_width+operand_b_width-1:0] result;
|
assign result = a * b;
|
assign result = a * b;
|
assign p = result[result_hi:result_lo];
|
assign p = result[result_hi:result_lo];
|
endmodule
|
endmodule
|
// shift unit
|
// shift unit
|
// supporting the following shift functions
|
// supporting the following shift functions
|
// SLL
|
// SLL
|
// SRL
|
// SRL
|
// SRA
|
// SRA
|
module vl_shift_unit_32( din, s, dout, opcode);
|
module vl_shift_unit_32( din, s, dout, opcode);
|
input [31:0] din; // data in operand
|
input [31:0] din; // data in operand
|
input [4:0] s; // shift operand
|
input [4:0] s; // shift operand
|
input [1:0] opcode;
|
input [1:0] opcode;
|
output [31:0] dout;
|
output [31:0] dout;
|
parameter opcode_sll = 2'b00;
|
parameter opcode_sll = 2'b00;
|
//parameter opcode_srl = 2'b01;
|
//parameter opcode_srl = 2'b01;
|
parameter opcode_sra = 2'b10;
|
parameter opcode_sra = 2'b10;
|
//parameter opcode_ror = 2'b11;
|
//parameter opcode_ror = 2'b11;
|
wire sll, sra;
|
wire sll, sra;
|
assign sll = opcode == opcode_sll;
|
assign sll = opcode == opcode_sll;
|
assign sra = opcode == opcode_sra;
|
assign sra = opcode == opcode_sra;
|
wire [15:1] s1;
|
wire [15:1] s1;
|
wire [3:0] sign;
|
wire [3:0] sign;
|
wire [7:0] tmp [0:3];
|
wire [7:0] tmp [0:3];
|
// first stage is multiplier based
|
// first stage is multiplier based
|
// shift operand as fractional 8.7
|
// shift operand as fractional 8.7
|
assign s1[15] = sll & s[2:0]==3'd7;
|
assign s1[15] = sll & s[2:0]==3'd7;
|
assign s1[14] = sll & s[2:0]==3'd6;
|
assign s1[14] = sll & s[2:0]==3'd6;
|
assign s1[13] = sll & s[2:0]==3'd5;
|
assign s1[13] = sll & s[2:0]==3'd5;
|
assign s1[12] = sll & s[2:0]==3'd4;
|
assign s1[12] = sll & s[2:0]==3'd4;
|
assign s1[11] = sll & s[2:0]==3'd3;
|
assign s1[11] = sll & s[2:0]==3'd3;
|
assign s1[10] = sll & s[2:0]==3'd2;
|
assign s1[10] = sll & s[2:0]==3'd2;
|
assign s1[ 9] = sll & s[2:0]==3'd1;
|
assign s1[ 9] = sll & s[2:0]==3'd1;
|
assign s1[ 8] = s[2:0]==3'd0;
|
assign s1[ 8] = s[2:0]==3'd0;
|
assign s1[ 7] = !sll & s[2:0]==3'd1;
|
assign s1[ 7] = !sll & s[2:0]==3'd1;
|
assign s1[ 6] = !sll & s[2:0]==3'd2;
|
assign s1[ 6] = !sll & s[2:0]==3'd2;
|
assign s1[ 5] = !sll & s[2:0]==3'd3;
|
assign s1[ 5] = !sll & s[2:0]==3'd3;
|
assign s1[ 4] = !sll & s[2:0]==3'd4;
|
assign s1[ 4] = !sll & s[2:0]==3'd4;
|
assign s1[ 3] = !sll & s[2:0]==3'd5;
|
assign s1[ 3] = !sll & s[2:0]==3'd5;
|
assign s1[ 2] = !sll & s[2:0]==3'd6;
|
assign s1[ 2] = !sll & s[2:0]==3'd6;
|
assign s1[ 1] = !sll & s[2:0]==3'd7;
|
assign s1[ 1] = !sll & s[2:0]==3'd7;
|
assign sign[3] = din[31] & sra;
|
assign sign[3] = din[31] & sra;
|
assign sign[2] = sign[3] & (&din[31:24]);
|
assign sign[2] = sign[3] & (&din[31:24]);
|
assign sign[1] = sign[2] & (&din[23:16]);
|
assign sign[1] = sign[2] & (&din[23:16]);
|
assign sign[0] = sign[1] & (&din[15:8]);
|
assign sign[0] = sign[1] & (&din[15:8]);
|
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
|
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
|
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte2 ( .a({sign[2], din[31:24] ,din[23:16], din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
|
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte2 ( .a({sign[2], din[31:24] ,din[23:16], din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
|
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte1 ( .a({sign[1], din[23:16] ,din[15:8], din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
|
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte1 ( .a({sign[1], din[23:16] ,din[15:8], din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
|
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte0 ( .a({sign[0], din[15:8] ,din[7:0], 8'h00}), .b({1'b0,s1}), .p(tmp[0]));
|
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte0 ( .a({sign[0], din[15:8] ,din[7:0], 8'h00}), .b({1'b0,s1}), .p(tmp[0]));
|
// second stage is multiplexer based
|
// second stage is multiplexer based
|
// shift on byte level
|
// shift on byte level
|
// mux byte 3
|
// mux byte 3
|
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
|
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
|
(sll & s[4:3]==2'b01) ? tmp[2] :
|
(sll & s[4:3]==2'b01) ? tmp[2] :
|
(sll & s[4:3]==2'b10) ? tmp[1] :
|
(sll & s[4:3]==2'b10) ? tmp[1] :
|
(sll & s[4:3]==2'b11) ? tmp[0] :
|
(sll & s[4:3]==2'b11) ? tmp[0] :
|
{8{sign[3]}};
|
{8{sign[3]}};
|
// mux byte 2
|
// mux byte 2
|
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
|
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
|
(sll & s[4:3]==2'b01) ? tmp[1] :
|
(sll & s[4:3]==2'b01) ? tmp[1] :
|
(sll & s[4:3]==2'b10) ? tmp[0] :
|
(sll & s[4:3]==2'b10) ? tmp[0] :
|
(sll & s[4:3]==2'b11) ? {8{1'b0}} :
|
(sll & s[4:3]==2'b11) ? {8{1'b0}} :
|
(s[4:3]==2'b01) ? tmp[3] :
|
(s[4:3]==2'b01) ? tmp[3] :
|
{8{sign[3]}};
|
{8{sign[3]}};
|
// mux byte 1
|
// mux byte 1
|
assign dout[15:8] = (s[4:3]==2'b00) ? tmp[1] :
|
assign dout[15:8] = (s[4:3]==2'b00) ? tmp[1] :
|
(sll & s[4:3]==2'b01) ? tmp[0] :
|
(sll & s[4:3]==2'b01) ? tmp[0] :
|
(sll & s[4:3]==2'b10) ? {8{1'b0}} :
|
(sll & s[4:3]==2'b10) ? {8{1'b0}} :
|
(sll & s[4:3]==2'b11) ? {8{1'b0}} :
|
(sll & s[4:3]==2'b11) ? {8{1'b0}} :
|
(s[4:3]==2'b01) ? tmp[2] :
|
(s[4:3]==2'b01) ? tmp[2] :
|
(s[4:3]==2'b10) ? tmp[3] :
|
(s[4:3]==2'b10) ? tmp[3] :
|
{8{sign[3]}};
|
{8{sign[3]}};
|
// mux byte 0
|
// mux byte 0
|
assign dout[7:0] = (s[4:3]==2'b00) ? tmp[0] :
|
assign dout[7:0] = (s[4:3]==2'b00) ? tmp[0] :
|
(sll) ? {8{1'b0}}:
|
(sll) ? {8{1'b0}}:
|
(s[4:3]==2'b01) ? tmp[1] :
|
(s[4:3]==2'b01) ? tmp[1] :
|
(s[4:3]==2'b10) ? tmp[2] :
|
(s[4:3]==2'b10) ? tmp[2] :
|
tmp[3];
|
tmp[3];
|
endmodule
|
endmodule
|
// logic unit
|
// logic unit
|
// supporting the following logic functions
|
// supporting the following logic functions
|
// a and b
|
// a and b
|
// a or b
|
// a or b
|
// a xor b
|
// a xor b
|
// not b
|
// not b
|
module vl_logic_unit( a, b, result, opcode);
|
module vl_logic_unit( a, b, result, opcode);
|
parameter width = 32;
|
parameter width = 32;
|
parameter opcode_and = 2'b00;
|
parameter opcode_and = 2'b00;
|
parameter opcode_or = 2'b01;
|
parameter opcode_or = 2'b01;
|
parameter opcode_xor = 2'b10;
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parameter opcode_xor = 2'b10;
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input [width-1:0] a,b;
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input [width-1:0] a,b;
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output [width-1:0] result;
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output [width-1:0] result;
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input [1:0] opcode;
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input [1:0] opcode;
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assign result = (opcode==opcode_and) ? a & b :
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assign result = (opcode==opcode_and) ? a & b :
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(opcode==opcode_or) ? a | b :
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(opcode==opcode_or) ? a | b :
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(opcode==opcode_xor) ? a ^ b :
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(opcode==opcode_xor) ? a ^ b :
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b;
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b;
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endmodule
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endmodule
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module vl_arith_unit ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
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module vl_arith_unit ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
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parameter width = 32;
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parameter width = 32;
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parameter opcode_add = 1'b0;
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parameter opcode_add = 1'b0;
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parameter opcode_sub = 1'b1;
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parameter opcode_sub = 1'b1;
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input [width-1:0] a,b;
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input [width-1:0] a,b;
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input c_in, add_sub, sign;
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input c_in, add_sub, sign;
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output [width-1:0] result;
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output [width-1:0] result;
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output c_out, z, ovfl;
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output c_out, z, ovfl;
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assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
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assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
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assign z = (result=={width{1'b0}});
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assign z = (result=={width{1'b0}});
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assign ovfl = ( a[width-1] & b[width-1] & ~result[width-1]) |
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assign ovfl = ( a[width-1] & b[width-1] & ~result[width-1]) |
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(~a[width-1] & ~b[width-1] & result[width-1]);
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(~a[width-1] & ~b[width-1] & result[width-1]);
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endmodule
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endmodule
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