URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Diff between revs 40 and 42

Rev 40	Rev 42
Line 445...	Line 445...
`output reg [width-1:0] dout;`	`output reg [width-1:0] dout;`
`integer i,j;`	`integer i,j;`
`always @ (a, sel)`	`always @ (a, sel)`
`begin`	`begin`
`dout = a[width-1:0] & {width{sel[0]}};`	`dout = a[width-1:0] & {width{sel[0]}};`
`for (i=nr_of_ports-2;i<nr_of_ports;i=i+1)`	`for (i=1;i<nr_of_ports;i=i+1)`
`for (j=0;j<32;j=j+1)`	`for (j=0;j<width;j=j+1)`
`dout[j] = (a[(i-1)*width + j] & sel[i]) \| dout[j];`	`dout[j] = (a[i*width + j] & sel[i]) \| dout[j];`
`end`	`end`
`endmodule`	`endmodule`
`module vl_mux2_andor ( a1, a0, sel, dout);`	`module vl_mux2_andor ( a1, a0, sel, dout);`
`parameter width = 32;`	`parameter width = 32;`
`localparam nr_of_ports = 2;`	`localparam nr_of_ports = 2;`