OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Diff between revs 45 and 46

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 45 Rev 46
Line 511... Line 511...
integer i,j;
integer i,j;
always @ (data)
always @ (data)
for (i=0;i<word_size/chunk_size;i=i+1) begin
for (i=0;i<word_size/chunk_size;i=i+1) begin
    parity[i] = parity_type;
    parity[i] = parity_type;
    for (j=0;j<chunk_size;j=j+1) begin
    for (j=0;j<chunk_size;j=j+1) begin
        parity[i] = data[i+j] ^ parity[i];
        parity[i] = data[i*chunk_size+j] ^ parity[i];
    end
    end
end
end
endmodule
endmodule
module vl_parity_check( data, parity, parity_error);
module vl_parity_check( data, parity, parity_error);
parameter word_size = 32;
parameter word_size = 32;
Line 528... Line 528...
integer i,j;
integer i,j;
always @ (data or parity)
always @ (data or parity)
for (i=0;i<word_size/chunk_size;i=i+1) begin
for (i=0;i<word_size/chunk_size;i=i+1) begin
    error_flag[i] = parity[i] ^ parity_type;
    error_flag[i] = parity[i] ^ parity_type;
    for (j=0;j<chunk_size;j=j+1) begin
    for (j=0;j<chunk_size;j=j+1) begin
        error_flag[i] = data[i+j] ^ error_flag[i];
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
    end
    end
end
end
assign parity_error = |error_flag;
assign parity_error = |error_flag;
endmodule
endmodule
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.