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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Diff between revs 46 and 48

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//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
 
`timescale 1 ns/100 ps
// Global buffer
// Global buffer
// usage:
// usage:
// use to enable global buffers for high fan out signals such as clock and reset
// use to enable global buffers for high fan out signals such as clock and reset
`timescale 1 ns/100 ps
 
// Version: 8.4 8.4.0.33
// Version: 8.4 8.4.0.33
module gbuf(GL,CLK);
module gbuf(GL,CLK);
output GL;
output GL;
input  CLK;
input  CLK;
    wire GND;
    wire GND;
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endmodule
endmodule
// LATCH
// LATCH
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
module vl_latch ( d, le, q, clk);
module vl_latch ( d, le, q, clk);
input d, le;
input d, le;
output q;
input clk;
input clk;/*
always @ (le or d)
   always @ (posedge direction_set or posedge direction_clr)
if le
     if (direction_clr)
    d <= q;
       direction <= going_empty;
 
     else
 
       direction <= going_full;*/
 
endmodule
endmodule
module vl_shreg ( d, q, clk, rst);
module vl_shreg ( d, q, clk, rst);
parameter depth = 10;
parameter depth = 10;
input d;
input d;
output q;
output q;
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        $readmemh(memory_file, rom);
        $readmemh(memory_file, rom);
     end
     end
   always @ (posedge clk)
   always @ (posedge clk)
     q <= rom[adr];
     q <= rom[adr];
endmodule
endmodule
/*
 
module vl_rom ( adr, q, clk);
 
parameter data_width = 32;
 
parameter addr_width = 4;
 
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
 
    {32'h18000000},
 
    {32'hA8200000},
 
    {32'hA8200000},
 
    {32'hA8200000},
 
    {32'h44003000},
 
    {32'h15000000},
 
    {32'h15000000},
 
    {32'h15000000},
 
    {32'h15000000},
 
    {32'h15000000},
 
    {32'h15000000},
 
    {32'h15000000},
 
    {32'h15000000},
 
    {32'h15000000},
 
    {32'h15000000},
 
    {32'h15000000}};
 
input [addr_width-1:0] adr;
 
output reg [data_width-1:0] q;
 
input clk;
 
always @ (posedge clk)
 
    q <= data[adr];
 
endmodule
 
*/
 
// Single port RAM
// Single port RAM
module vl_ram ( d, adr, we, q, clk);
module vl_ram ( d, adr, we, q, clk);
   parameter data_width = 32;
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter addr_width = 8;
   input [(data_width-1):0]      d;
   input [(data_width-1):0]      d;
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   end
   end
   endgenerate
   endgenerate
   always @ (posedge clk)
   always @ (posedge clk)
      q <= ram[adr];
      q <= ram[adr];
endmodule
endmodule
// Dual port RAM
 
// ACTEL FPGA should not use logic to handle rw collision
// ACTEL FPGA should not use logic to handle rw collision
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
   parameter data_width = 32;
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter addr_width = 8;
   input [(data_width-1):0]      d_a;
   input [(data_width-1):0]      d_a;
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    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
vl_fifo_cmp_async
vl_fifo_cmp_async
    # (.addr_width(addr_width))
    # (.addr_width(addr_width))
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
endmodule
endmodule
 
module vl_reg_file (
 
    a1, a2, a3, wd3, we3, rd1, rd2, clk
 
);
 
parameter data_width = 32;
 
parameter addr_width = 5;
 
input [addr_width-1:0] a1, a2, a3;
 
input [data_width-1:0] wd3;
 
input we3;
 
output [data_width-1:0] rd1, rd2;
 
input clk;
 
reg [data_width-1:0] wd3_reg;
 
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
 
reg we3_reg;
 
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
 
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
 
always @ (posedge clk or posedge rst)
 
if (rst)
 
    {wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
 
else
 
    {wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
 
    always @ (negedge clk)
 
    if (we3_reg)
 
        ram1[a3_reg] <= wd3;
 
    always @ (posedge clk)
 
        a1_reg <= a1;
 
    assign rd1 = ram1[a1_reg];
 
    always @ (negedge clk)
 
    if (we3_reg)
 
        ram2[a3_reg] <= wd3;
 
    always @ (posedge clk)
 
        a2_reg <= a2;
 
    assign rd2 = ram2[a2_reg];
 
endmodule
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile library, wishbone stuff                           ////
////  Versatile library, wishbone stuff                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
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    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
endmodule
endmodule
// WB ROM
// WB ROM
 
module vl_wb_b4_rom (
 
    wb_adr_i, wb_stb_i, wb_cyc_i,
 
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
 
    parameter dat_width = 32;
 
    parameter dat_default = 32'h15000000;
 
    parameter adr_width = 32;
 
/*
 
`ifndef ROM
 
`define ROM "rom.v"
 
`endif
 
*/
 
    input [adr_width-1:2]   wb_adr_i;
 
    input                   wb_stb_i;
 
    input                   wb_cyc_i;
 
    output [dat_width-1:0]  wb_dat_o;
 
    reg [dat_width-1:0]     wb_dat_o;
 
    output                  wb_ack_o;
 
    reg                     wb_ack_o;
 
    output                  stall_o;
 
    input                   wb_clk;
 
    input                   wb_rst;
 
always @ (posedge wb_clk or posedge wb_rst)
 
    if (wb_rst)
 
        wb_dat_o <= {dat_width{1'b0}};
 
    else
 
         case (wb_adr_i[adr_width-1:2])
 
`ifdef ROM
 
`include `ROM
 
`endif
 
           default:
 
             wb_dat_o <= dat_default;
 
         endcase // case (wb_adr_i)
 
always @ (posedge wb_clk or posedge wb_rst)
 
    if (wb_rst)
 
        wb_ack_o <= 1'b0;
 
    else
 
        wb_ack_o <= wb_stb_i & wb_cyc_i;
 
assign stall_o = 1'b0;
 
endmodule
 
// WB ROM
module vl_wb_boot_rom (
module vl_wb_boot_rom (
    wb_adr_i, wb_stb_i, wb_cyc_i,
    wb_adr_i, wb_stb_i, wb_cyc_i,
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
    parameter adr_hi = 31;
    parameter adr_hi = 31;
    parameter adr_lo = 28;
    parameter adr_lo = 28;
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assign result = (opcode==opcode_and) ? a & b :
assign result = (opcode==opcode_and) ? a & b :
                (opcode==opcode_or)  ? a | b :
                (opcode==opcode_or)  ? a | b :
                (opcode==opcode_xor) ? a ^ b :
                (opcode==opcode_xor) ? a ^ b :
                b;
                b;
endmodule
endmodule
module vl_arith_unit ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
 
parameter width = 32;
 
parameter opcode_add = 1'b0;
 
parameter opcode_sub = 1'b1;
 
input [width-1:0] a,b;
 
input c_in, add_sub, sign;
 
output [width-1:0] result;
 
output c_out, z, ovfl;
 
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
 
assign z = (result=={width{1'b0}});
 
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
 
               (~a[width-1] & ~b[width-1] &  result[width-1]);
 
endmodule
 
 
 
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