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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Diff between revs 53 and 54

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endgenerate
endgenerate
always @ (posedge wb_clk or posedge wb_rst)
always @ (posedge wb_clk or posedge wb_rst)
if (rst)
if (rst)
    wb_ack_o <= 1'b0;
    wb_ack_o <= 1'b0;
else
else
    wb_ack_o <= wb_stb_i & wb_cyc_i
    wb_ack_o <= wb_stb_i & wb_cyc_i;
assign wb_stall_o = 1'b0;
assign wb_stall_o = 1'b0;
endmodule
endmodule
// WB ROM
// WB ROM
module vl_wb_b4_rom (
module vl_wb_b4_rom (
    wb_adr_i, wb_stb_i, wb_cyc_i,
    wb_adr_i, wb_stb_i, wb_cyc_i,

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