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// default SYN_KEEP definition
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Versatile library, clock and reset ////
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//// Versatile library, clock and reset ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
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// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
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module vl_latch ( d, le, q, clk);
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module vl_latch ( d, le, q, clk);
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input d, le;
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input d, le;
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input clk;
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input clk;
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always @ (le or d)
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always @ (le or d)
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if le
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if (le)
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d <= q;
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d <= q;
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endmodule
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endmodule
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module vl_shreg ( d, q, clk, rst);
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module vl_shreg ( d, q, clk, rst);
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parameter depth = 10;
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parameter depth = 10;
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input d;
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input d;
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input [(addr_width/4)-1:0] be;
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input [(addr_width/4)-1:0] be;
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input we;
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input we;
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output reg [(data_width-1):0] q;
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output reg [(data_width-1):0] q;
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input clk;
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input clk;
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reg [data_width-1:0] ram [(1<<addr_width)-1:0];
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reg [data_width-1:0] ram [(1<<addr_width)-1:0];
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parameter init = 0;
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parameter memory_init = 0;
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parameter memory_file = "vl_ram.vmem";
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parameter memory_file = "vl_ram.vmem";
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generate if (init) begin : init_mem
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generate if (memory_init) begin : init_mem
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initial
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initial
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begin
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begin
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$readmemh(memory_file, ram);
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$readmemh(memory_file, ram);
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end
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end
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end
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end
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endgenerate
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endgenerate
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`ifdef SYSTEMVERILOG
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// use a multi-dimensional packed array
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//to model individual bytes within the word
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logic [dat_width/8-1:0][7:0] ram[0:1<<(adr_width-2)-1];// # words = 1 << address width
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always_ff@(posedge clk)
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begin
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if(we) begin // note: we should have a for statement to support any bus width
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if(be[3]) ram[adr[adr_size-2:0]][3] <= d[31:24];
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if(be[2]) ram[adr[adr_size-2:0]][2] <= d[23:16];
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if(be[1]) ram[adr[adr_size-2:0]][1] <= d[15:8];
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if(be[0]) ram[adr[adr_size-2:0]][0] <= d[7:0];
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end
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q <= ram[raddr];
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end
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`else
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genvar i;
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genvar i;
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generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
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generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
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always @ (posedge clk)
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always @ (posedge clk)
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if (we & be[i])
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if (we & be[i])
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ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
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ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
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end
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end
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endgenerate
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endgenerate
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always @ (posedge clk)
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always @ (posedge clk)
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q <= ram[adr];
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q <= ram[adr];
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`endif
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endmodule
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endmodule
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// ACTEL FPGA should not use logic to handle rw collision
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// ACTEL FPGA should not use logic to handle rw collision
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module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
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module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
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parameter data_width = 32;
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parameter data_width = 32;
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parameter addr_width = 8;
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parameter addr_width = 8;
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endmodule
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endmodule
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// WB RAM with byte enable
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// WB RAM with byte enable
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module vl_wb_b3_ram_be (
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module vl_wb_b3_ram_be (
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wb_dat_i, wb_adr_i, wb_cti_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
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wb_dat_i, wb_adr_i, wb_cti_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
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wb_dat_o, wb_ack_o, wb_clk, wb_rst);
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wb_dat_o, wb_ack_o, wb_clk, wb_rst);
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parameter dat_width = 32;
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parameter nr_of_ports = 3;
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parameter adr_width = 8;
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parameter wb_arbiter_type = 1;
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input [dat_width-1:0] wb_dat_i;
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parameter adr_size = 26;
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input [adr_width-1:0] wb_adr_i;
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parameter adr_lo = 2;
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input [2:0] wb_cti_i;
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parameter dat_size = 32;
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input [dat_width/8-1:0] wb_sel_i;
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parameter memory_init = 1;
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input wb_we_i, wb_stb_i, wb_cyc_i;
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parameter memory_file = "vl_ram.vmem";
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output [dat_width-1:0] wb_dat_o;
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localparam aw = (adr_size - adr_lo) * nr_of_ports;
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reg [dat_width-1:0] wb_dat_o;
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localparam dw = dat_size * nr_of_ports;
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output wb_stall_o;
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localparam sw = dat_size/8 * nr_of_ports;
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localparam cw = 3 * nr_of_ports;
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localparam bw = 2 * nr_of_ports;
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input [dw-1:0] wb_dat_i;
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input [aw-1:0] wb_adr_i;
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input [cw-1:0] wb_cti_i;
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input [sw-1:0] wb_sel_i;
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input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i;
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output [dw-1:0] wb_dat_o;
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reg [dw-1:0] wb_dat_o;
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output wb_ack_o;
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output wb_ack_o;
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reg wb_ack_o;
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reg wb_ack_o;
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input wb_clk, wb_rst;
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input wb_clk, wb_rst;
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wire [dat_width/8-1:0] cke;
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wire [sw-1:0] cke;
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// local wb slave
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wire [dat_size-1:0] wbs_dat_i;
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wire [adr_size-1:0] wbs_adr_i;
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wire [2:0] wbs_cti_i;
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wire [(dat_size/8)-1:0] wbs_sel_i;
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wire wbs_we_i, wbs_stb_i, wbs_cyc_i;
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wire [dat_size-1:0] wbs_dat_o;
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reg wbs_ack_o;
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generate
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generate
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if (dat_width==32) begin
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if (nr_of_ports == 1) begin
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reg [7:0] ram3 [1<<(adr_width-2)-1:0];
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assign wbs_dat_i = wb_dat_i;
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reg [7:0] ram2 [1<<(adr_width-2)-1:0];
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assign wbs_adr_i = wb_adr_i;
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reg [7:0] ram1 [1<<(adr_width-2)-1:0];
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assign wbs_cti_i = wb_cti_i;
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reg [7:0] ram0 [1<<(adr_width-2)-1:0];
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assign wbs_sel_i = wb_sel_i;
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assign cke = wb_sel_i & {(dat_width/8){wb_we_i}};
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assign wbs_we_i = wb_we_i;
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always @ (posedge wb_clk)
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assign wbs_stb_i = wb_stb_i;
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begin
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assign wbs_cyc_i = wb_cyc_i;
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if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
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assign wb_dat_o = wbs_dat_o;
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if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
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assign wb_ack_o = wbs_ack_o;
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if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
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if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
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end
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always @ (posedge wb_clk or posedge wb_rst)
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begin
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if (wb_rst)
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wb_dat_o <= 32'h0;
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else
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wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
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end
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end
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endgenerate
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generate
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if (nr_of_ports > 1 & wb_arbiter_type == 1) begin
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vl_wb3_arbiter_type1 wb_arbiter0(
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.wbm_dat_o(wb_dat_i),
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.wbm_adr_o(wb_adr_i),
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.wbm_sel_o(wb_sel_i),
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.wbm_cti_o(wb_cti_i),
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.wbm_bte_o(wb_bte_i),
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.wbm_we_o(wb_we_i),
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.wbm_stb_o(wb_stb_i),
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.wbm_cyc_o(wb_cyc_i),
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.wbm_dat_i(wb_dat_o),
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.wbm_ack_i(wb_ack_o),
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.wbm_err_i(),
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.wbm_rty_i(),
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.wbs_dat_i(wbs_dat_i),
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.wbs_adr_i(wbs_adr_i),
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.wbs_sel_i(wbs_sel_i),
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.wbs_cti_i(wbs_cti_i),
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.wbs_bte_i(wbs_bte_i),
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.wbs_we_i(wbs_we_i),
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.wbs_stb_i(wbs_stb_i),
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.wbs_cyc_i(wbs_cyc_i),
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.wbs_dat_o(wbs_dat_o),
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.wbs_ack_o(wbs_ack_o),
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.wbs_err_o(1'b0),
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.wbs_rty_o(1'b0),
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.wb_clk(wb_clk),
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.wb_rst(wb_rst)
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);
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end
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end
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endgenerate
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endgenerate
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vl_ram_be # (
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.data_width(dat_size),
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.addr_width(adr_size),
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.memory_init(1),
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.memory_file("memory_file"))
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ram0(
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.d(wbs_dat_i),
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.adr(wbs_adr_i[adr_size-1:2]),
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.be(wbs_sel_i),
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.we(wbs_we_i),
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.q(wbs_dat_o),
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.clk(wb_clk)
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);
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always @ (posedge wb_clk or posedge wb_rst)
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always @ (posedge wb_clk or posedge wb_rst)
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if (wb_rst)
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if (wb_rst)
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wb_ack_o <= 1'b0;
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wbs_ack_o <= 1'b0;
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else
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else
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if (wb_cti_i=3'b000 | wb_cti_i=3'b111)
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if (wbs_cti_i==3'b000 | wbs_cti_i==3'b111)
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wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o;
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wbs_ack_o <= wbs_stb_i & wbs_cyc_i & !wbs_ack_o;
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else
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else
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wb_ack_o <= wb_stb_i & wb_cyc_i;
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wbs_ack_o <= wbs_stb_i & wbs_cyc_i;
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endmodule
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endmodule
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// WB RAM with byte enable
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// WB RAM with byte enable
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module vl_wb_b4_ram_be (
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module vl_wb_b4_ram_be (
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wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
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wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
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wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
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wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
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