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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Diff between revs 59 and 60

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// default SYN_KEEP definition
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile library, clock and reset                          ////
////  Versatile library, clock and reset                          ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
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// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
module vl_latch ( d, le, q, clk);
module vl_latch ( d, le, q, clk);
input d, le;
input d, le;
input clk;
input clk;
always @ (le or d)
always @ (le or d)
if le
if (le)
    d <= q;
    d <= q;
endmodule
endmodule
module vl_shreg ( d, q, clk, rst);
module vl_shreg ( d, q, clk, rst);
parameter depth = 10;
parameter depth = 10;
input d;
input d;
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   input [(addr_width/4)-1:0]    be;
   input [(addr_width/4)-1:0]    be;
   input                         we;
   input                         we;
   output reg [(data_width-1):0] q;
   output reg [(data_width-1):0] q;
   input                         clk;
   input                         clk;
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
   parameter init = 0;
   parameter memory_init = 0;
   parameter memory_file = "vl_ram.vmem";
   parameter memory_file = "vl_ram.vmem";
   generate if (init) begin : init_mem
   generate if (memory_init) begin : init_mem
   initial
   initial
     begin
     begin
        $readmemh(memory_file, ram);
        $readmemh(memory_file, ram);
     end
     end
   end
   end
   endgenerate
   endgenerate
 
`ifdef SYSTEMVERILOG
 
// use a multi-dimensional packed array
 
//to model individual bytes within the word
 
logic [dat_width/8-1:0][7:0] ram[0:1<<(adr_width-2)-1];// # words = 1 << address width
 
always_ff@(posedge clk)
 
begin
 
    if(we) begin // note: we should have a for statement to support any bus width
 
        if(be[3]) ram[adr[adr_size-2:0]][3] <= d[31:24];
 
        if(be[2]) ram[adr[adr_size-2:0]][2] <= d[23:16];
 
        if(be[1]) ram[adr[adr_size-2:0]][1] <= d[15:8];
 
        if(be[0]) ram[adr[adr_size-2:0]][0] <= d[7:0];
 
    end
 
    q <= ram[raddr];
 
end
 
`else
   genvar i;
   genvar i;
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
      always @ (posedge clk)
      always @ (posedge clk)
      if (we & be[i])
      if (we & be[i])
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
   end
   end
   endgenerate
   endgenerate
   always @ (posedge clk)
   always @ (posedge clk)
      q <= ram[adr];
      q <= ram[adr];
 
`endif
endmodule
endmodule
        // ACTEL FPGA should not use logic to handle rw collision
        // ACTEL FPGA should not use logic to handle rw collision
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
   parameter data_width = 32;
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter addr_width = 8;
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endmodule
endmodule
// WB RAM with byte enable
// WB RAM with byte enable
module vl_wb_b3_ram_be (
module vl_wb_b3_ram_be (
    wb_dat_i, wb_adr_i, wb_cti_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
    wb_dat_i, wb_adr_i, wb_cti_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
    wb_dat_o, wb_ack_o, wb_clk, wb_rst);
    wb_dat_o, wb_ack_o, wb_clk, wb_rst);
    parameter dat_width = 32;
parameter nr_of_ports = 3;
    parameter adr_width = 8;
parameter wb_arbiter_type = 1;
input [dat_width-1:0] wb_dat_i;
parameter adr_size = 26;
input [adr_width-1:0] wb_adr_i;
parameter adr_lo   = 2;
input [2:0] wb_cti_i;
parameter dat_size = 32;
input [dat_width/8-1:0] wb_sel_i;
parameter memory_init = 1;
input wb_we_i, wb_stb_i, wb_cyc_i;
parameter memory_file = "vl_ram.vmem";
output [dat_width-1:0] wb_dat_o;
localparam aw = (adr_size - adr_lo) * nr_of_ports;
reg [dat_width-1:0] wb_dat_o;
localparam dw = dat_size * nr_of_ports;
output wb_stall_o;
localparam sw = dat_size/8 * nr_of_ports;
 
localparam cw = 3 * nr_of_ports;
 
localparam bw = 2 * nr_of_ports;
 
input [dw-1:0] wb_dat_i;
 
input [aw-1:0] wb_adr_i;
 
input [cw-1:0] wb_cti_i;
 
input [sw-1:0] wb_sel_i;
 
input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i;
 
output [dw-1:0] wb_dat_o;
 
reg [dw-1:0] wb_dat_o;
output wb_ack_o;
output wb_ack_o;
reg wb_ack_o;
reg wb_ack_o;
input wb_clk, wb_rst;
input wb_clk, wb_rst;
wire [dat_width/8-1:0] cke;
wire [sw-1:0] cke;
 
// local wb slave
 
wire [dat_size-1:0] wbs_dat_i;
 
wire [adr_size-1:0] wbs_adr_i;
 
wire [2:0] wbs_cti_i;
 
wire [(dat_size/8)-1:0] wbs_sel_i;
 
wire  wbs_we_i, wbs_stb_i, wbs_cyc_i;
 
wire [dat_size-1:0] wbs_dat_o;
 
reg wbs_ack_o;
generate
generate
if (dat_width==32) begin
if (nr_of_ports == 1) begin
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
    assign wbs_dat_i = wb_dat_i;
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
    assign wbs_adr_i = wb_adr_i;
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
    assign wbs_cti_i = wb_cti_i;
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
    assign wbs_sel_i = wb_sel_i;
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}};
    assign wbs_we_i  = wb_we_i;
    always @ (posedge wb_clk)
    assign wbs_stb_i = wb_stb_i;
    begin
    assign wbs_cyc_i = wb_cyc_i;
        if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
    assign wb_dat_o  = wbs_dat_o;
        if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
    assign wb_ack_o  = wbs_ack_o;
        if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
 
        if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
 
    end
 
    always @ (posedge wb_clk or posedge wb_rst)
 
    begin
 
        if (wb_rst)
 
            wb_dat_o <= 32'h0;
 
        else
 
            wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
 
    end
    end
 
endgenerate
 
generate
 
if (nr_of_ports > 1 & wb_arbiter_type == 1) begin
 
vl_wb3_arbiter_type1 wb_arbiter0(
 
    .wbm_dat_o(wb_dat_i),
 
    .wbm_adr_o(wb_adr_i),
 
    .wbm_sel_o(wb_sel_i),
 
    .wbm_cti_o(wb_cti_i),
 
    .wbm_bte_o(wb_bte_i),
 
    .wbm_we_o(wb_we_i),
 
    .wbm_stb_o(wb_stb_i),
 
    .wbm_cyc_o(wb_cyc_i),
 
    .wbm_dat_i(wb_dat_o),
 
    .wbm_ack_i(wb_ack_o),
 
    .wbm_err_i(),
 
    .wbm_rty_i(),
 
    .wbs_dat_i(wbs_dat_i),
 
    .wbs_adr_i(wbs_adr_i),
 
    .wbs_sel_i(wbs_sel_i),
 
    .wbs_cti_i(wbs_cti_i),
 
    .wbs_bte_i(wbs_bte_i),
 
    .wbs_we_i(wbs_we_i),
 
    .wbs_stb_i(wbs_stb_i),
 
    .wbs_cyc_i(wbs_cyc_i),
 
    .wbs_dat_o(wbs_dat_o),
 
    .wbs_ack_o(wbs_ack_o),
 
    .wbs_err_o(1'b0),
 
    .wbs_rty_o(1'b0),
 
    .wb_clk(wb_clk),
 
    .wb_rst(wb_rst)
 
);
end
end
endgenerate
endgenerate
 
vl_ram_be # (
 
    .data_width(dat_size),
 
    .addr_width(adr_size),
 
    .memory_init(1),
 
    .memory_file("memory_file"))
 
ram0(
 
    .d(wbs_dat_i),
 
    .adr(wbs_adr_i[adr_size-1:2]),
 
    .be(wbs_sel_i),
 
    .we(wbs_we_i),
 
    .q(wbs_dat_o),
 
    .clk(wb_clk)
 
);
always @ (posedge wb_clk or posedge wb_rst)
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
if (wb_rst)
    wb_ack_o <= 1'b0;
    wbs_ack_o <= 1'b0;
else
else
    if (wb_cti_i=3'b000 | wb_cti_i=3'b111)
    if (wbs_cti_i==3'b000 | wbs_cti_i==3'b111)
        wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o;
        wbs_ack_o <= wbs_stb_i & wbs_cyc_i & !wbs_ack_o;
    else
    else
        wb_ack_o <= wb_stb_i & wb_cyc_i;
        wbs_ack_o <= wbs_stb_i & wbs_cyc_i;
endmodule
endmodule
// WB RAM with byte enable
// WB RAM with byte enable
module vl_wb_b4_ram_be (
module vl_wb_b4_ram_be (
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
    wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
    wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);

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