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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Diff between revs 65 and 66

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Rev 65 Rev 66
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input [cw-1:0] wb_cti_i;
input [cw-1:0] wb_cti_i;
input [bw-1:0] wb_bte_i;
input [bw-1:0] wb_bte_i;
input [sw-1:0] wb_sel_i;
input [sw-1:0] wb_sel_i;
input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i;
input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i;
output [dw-1:0] wb_dat_o;
output [dw-1:0] wb_dat_o;
output wb_ack_o;
output [nr_of_ports-1:0] wb_ack_o;
input wb_clk, wb_rst;
input wb_clk, wb_rst;
wire [sw-1:0] cke;
wire [sw-1:0] cke;
// local wb slave
// local wb slave
wire [dat_size-1:0] wbs_dat_i;
wire [dat_size-1:0] wbs_dat_i;
wire [adr_size-1:0] wbs_adr_i;
wire [adr_size-1:0] wbs_adr_i;

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