| Line 1275... |
Line 1275... |
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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/// ROM
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/// ROM
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module vl_rom ( a, q, clk);
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module vl_rom_init ( adr, q, clk);
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parameter data_width = 32;
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parameter addr_width = 8;
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input [(addr_width-1):0] adr;
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output reg [(data_width-1):0] q;
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input clk;
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reg [data_width-1:0] rom [(1<<addr_width)-1:0];
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parameter memory_file = "vl_rom.vmem";
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initial
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begin
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$readmemh(memory_file, rom);
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end
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always @ (posedge clk)
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q <= rom[adr];
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endmodule
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module vl_rom ( adr, q, clk);
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parameter data_width = 32;
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parameter data_width = 32;
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parameter addr_width = 4;
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parameter addr_width = 4;
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parameter [0:1>>addr_width-1] data [data_width-1:0] = {
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parameter [0:1>>addr_width-1] data [data_width-1:0] = {
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{32'h18000000},
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{32'h18000000},
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{32'hA8200000},
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{32'hA8200000},
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| Line 1295... |
Line 1310... |
{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000},
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{32'h15000000}};
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{32'h15000000}};
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input [addr_width-1:0] a;
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input [addr_width-1:0] adr;
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output reg [data_width-1:0] q;
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output reg [data_width-1:0] q;
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input clk;
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input clk;
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always @ (posedge clk)
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always @ (posedge clk)
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q <= data[a];
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q <= data[adr];
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endmodule
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endmodule
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// Single port RAM
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// Single port RAM
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module vl_ram ( d, adr, we, q, clk);
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module vl_ram ( d, adr, we, q, clk);
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parameter data_width = 32;
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parameter data_width = 32;
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parameter addr_width = 8;
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parameter addr_width = 8;
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| Line 1311... |
Line 1326... |
input [(addr_width-1):0] adr;
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input [(addr_width-1):0] adr;
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input we;
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input we;
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output reg [(data_width-1):0] q;
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output reg [(data_width-1):0] q;
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input clk;
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input clk;
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reg [data_width-1:0] ram [(1<<addr_width)-1:0];
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reg [data_width-1:0] ram [(1<<addr_width)-1:0];
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parameter init = 0;
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parameter memory_file = "vl_ram.vmem";
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generate if (init) begin : init_mem
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initial
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begin
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$readmemh(memory_file, ram);
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end
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end
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endgenerate
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always @ (posedge clk)
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always @ (posedge clk)
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begin
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begin
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if (we)
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if (we)
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ram[adr] <= d;
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ram[adr] <= d;
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q <= ram[adr];
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q <= ram[adr];
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end
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end
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endmodule
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endmodule
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module vl_ram_be ( d, adr, be, we, q, clk);
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parameter data_width = 32;
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parameter addr_width = 8;
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input [(data_width-1):0] d;
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input [(addr_width-1):0] adr;
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input [(addr_width/4)-1:0] be;
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input we;
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output reg [(data_width-1):0] q;
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input clk;
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reg [data_width-1:0] ram [(1<<addr_width)-1:0];
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parameter init = 0;
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parameter memory_file = "vl_ram.vmem";
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generate if (init) begin : init_mem
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initial
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begin
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$readmemh(memory_file, ram);
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end
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end
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endgenerate
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genvar i;
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generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
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always @ (posedge clk)
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if (we & be[i])
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ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
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end
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endgenerate
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always @ (posedge clk)
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q <= ram[adr];
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endmodule
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// Dual port RAM
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// Dual port RAM
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// ACTEL FPGA should not use logic to handle rw collision
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// ACTEL FPGA should not use logic to handle rw collision
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module vl_dual_port_ram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
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module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
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parameter data_width = 32;
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parameter data_width = 32;
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parameter addr_width = 8;
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parameter addr_width = 8;
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input [(data_width-1):0] d_a;
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input [(data_width-1):0] d_a;
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input [(addr_width-1):0] adr_a;
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input [(addr_width-1):0] adr_a;
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input [(addr_width-1):0] adr_b;
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input [(addr_width-1):0] adr_b;
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input we_a;
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input we_a;
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output [(data_width-1):0] q_b;
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output [(data_width-1):0] q_b;
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input clk_a, clk_b;
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input clk_a, clk_b;
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reg [(addr_width-1):0] adr_b_reg;
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reg [(addr_width-1):0] adr_b_reg;
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reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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parameter init = 0;
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parameter memory_file = "vl_ram.vmem";
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generate if (init) begin : init_mem
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initial
|
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begin
|
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$readmemh(memory_file, ram);
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end
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end
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endgenerate
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always @ (posedge clk_a)
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always @ (posedge clk_a)
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if (we_a)
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if (we_a)
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ram[adr_a] <= d_a;
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ram[adr_a] <= d_a;
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always @ (posedge clk_b)
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always @ (posedge clk_b)
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adr_b_reg <= adr_b;
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adr_b_reg <= adr_b;
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assign q_b = ram[adr_b_reg];
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assign q_b = ram[adr_b_reg];
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endmodule
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endmodule
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module vl_dual_port_ram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
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module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
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parameter data_width = 32;
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parameter data_width = 32;
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parameter addr_width = 8;
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parameter addr_width = 8;
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input [(data_width-1):0] d_a;
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input [(data_width-1):0] d_a;
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input [(addr_width-1):0] adr_a;
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input [(addr_width-1):0] adr_a;
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input [(addr_width-1):0] adr_b;
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input [(addr_width-1):0] adr_b;
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| Line 1350... |
Line 1412... |
output [(data_width-1):0] q_b;
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output [(data_width-1):0] q_b;
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output reg [(data_width-1):0] q_a;
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output reg [(data_width-1):0] q_a;
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input clk_a, clk_b;
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input clk_a, clk_b;
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reg [(data_width-1):0] q_b;
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reg [(data_width-1):0] q_b;
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reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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parameter init = 0;
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parameter memory_file = "vl_ram.vmem";
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generate if (init) begin : init_mem
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initial
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begin
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$readmemh(memory_file, ram);
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end
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end
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endgenerate
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always @ (posedge clk_a)
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always @ (posedge clk_a)
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begin
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begin
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q_a <= ram[adr_a];
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q_a <= ram[adr_a];
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if (we_a)
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if (we_a)
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ram[adr_a] <= d_a;
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ram[adr_a] <= d_a;
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end
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end
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always @ (posedge clk_b)
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always @ (posedge clk_b)
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q_b <= ram[adr_b];
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q_b <= ram[adr_b];
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endmodule
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endmodule
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module vl_dual_port_ram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, d_b, we_b, clk_b );
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module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
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parameter data_width = 32;
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parameter data_width = 32;
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parameter addr_width = 8;
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parameter addr_width = 8;
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input [(data_width-1):0] d_a;
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input [(data_width-1):0] d_a;
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input [(addr_width-1):0] adr_a;
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input [(addr_width-1):0] adr_a;
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input [(addr_width-1):0] adr_b;
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input [(addr_width-1):0] adr_b;
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| Line 1373... |
Line 1444... |
output reg [(data_width-1):0] q_a;
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output reg [(data_width-1):0] q_a;
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input we_b;
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input we_b;
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input clk_a, clk_b;
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input clk_a, clk_b;
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reg [(data_width-1):0] q_b;
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reg [(data_width-1):0] q_b;
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reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
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parameter init = 0;
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parameter memory_file = "vl_ram.vmem";
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generate if (init) begin : init_mem
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initial
|
|
begin
|
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$readmemh(memory_file, ram);
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end
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end
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endgenerate
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always @ (posedge clk_a)
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always @ (posedge clk_a)
|
begin
|
begin
|
q_a <= ram[adr_a];
|
q_a <= ram[adr_a];
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if (we_a)
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if (we_a)
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ram[adr_a] <= d_a;
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ram[adr_a] <= d_a;
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| Line 1470... |
Line 1550... |
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
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wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
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vl_fifo_1r1w_async (
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vl_fifo_1r1w_async (
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d, wr, fifo_full, wr_clk, wr_rst,
|
d, wr, fifo_full, wr_clk, wr_rst,
|
q, rd, fifo_empty, rd_clk, rd_rst
|
q, rd, fifo_empty, rd_clk, rd_rst
|
);
|
);
|
adr_gen
|
cnt_gray_ce_bin
|
# ( .length(addr_width))
|
# ( .length(addr_width))
|
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
|
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
|
adr_gen
|
cnt_gray_ce_bin
|
# (.length(addr_width))
|
# (.length(addr_width))
|
fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
|
fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
|
vl_dual_port_ram_1r1w
|
vl_dpram_1r1w
|
# (.data_width(data_width), .addr_width(addr_width))
|
# (.data_width(data_width), .addr_width(addr_width))
|
dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
|
dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
|
vl_fifo_cmp_async
|
vl_fifo_cmp_async
|
# (.addr_width(addr_width))
|
# (.addr_width(addr_width))
|
cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
|
cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
|
| Line 1559... |
Line 1639... |
// adr_gen
|
// adr_gen
|
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
|
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
|
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
|
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
|
// dpram
|
// dpram
|
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
|
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
|
adr_gen
|
cnt_gray_ce_bin
|
# ( .length(addr_width))
|
# ( .length(addr_width))
|
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
|
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
|
adr_gen
|
cnt_gray_ce_bin
|
# (.length(addr_width))
|
# (.length(addr_width))
|
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
|
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
|
adr_gen
|
cnt_gray_ce_bin
|
# ( .length(addr_width))
|
# ( .length(addr_width))
|
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
|
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
|
adr_gen
|
cnt_gray_ce_bin
|
# (.length(addr_width))
|
# (.length(addr_width))
|
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
|
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
|
// mux read or write adr to DPRAM
|
// mux read or write adr to DPRAM
|
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
|
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
|
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
|
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
|
vfifo_dual_port_ram_dc_dw
|
vl_dp_ram_2r2w
|
# (.data_width(data_width), .addr_width(addr_width+1))
|
# (.data_width(data_width), .addr_width(addr_width+1))
|
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
|
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
|
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
|
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
|
vl_fifo_async_cmp
|
vl_fifo_async_cmp
|
# (.addr_width(addr_width))
|
# (.addr_width(addr_width))
|
cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
|
cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
|
versatile_fifo_async_cmp
|
vl_fifo_async_cmp
|
# (.addr_width(addr_width))
|
# (.addr_width(addr_width))
|
cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
|
cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
|
endmodule
|
endmodule
|
|
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No newline at end of file
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No newline at end of file
|
