OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Diff between revs 6 and 7

Go to most recent revision | Only display areas with differences | Details | Blame | View Log

Rev 6 Rev 7
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile library, clock and reset                          ////
////  Versatile library, clock and reset                          ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Logic related to clock and reset                            ////
////  Logic related to clock and reset                            ////
////                                                              ////
////                                                              ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add more different registers                             ////
////   - add more different registers                             ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// Global buffer
// Global buffer
// usage:
// usage:
// use to enable global buffers for high fan out signals such as clock and reset
// use to enable global buffers for high fan out signals such as clock and reset
`timescale 1 ns/100 ps
`timescale 1 ns/100 ps
// Version: 8.4 8.4.0.33
// Version: 8.4 8.4.0.33
module gbuf(GL,CLK);
module gbuf(GL,CLK);
output GL;
output GL;
input  CLK;
input  CLK;
    wire GND;
    wire GND;
    GND GND_1_net(.Y(GND));
    GND GND_1_net(.Y(GND));
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
endmodule
endmodule
`timescale 1 ns/1 ns
`timescale 1 ns/1 ns
module vl_gbuf ( i, o);
module vl_gbuf ( i, o);
input i;
input i;
output o;
output o;
`ifdef SIM_GBUF
`ifdef SIM_GBUF
assign o=i;
assign o=i;
`else
`else
gbuf gbuf_i0 ( .CLK(i), .GL(o));
gbuf gbuf_i0 ( .CLK(i), .GL(o));
`endif
`endif
endmodule
endmodule
 //ACTEL
 //ACTEL
// sync reset
// sync reset
// input active lo async reset, normally from external reset generetaor and/or switch
// input active lo async reset, normally from external reset generetaor and/or switch
// output active high global reset sync with two DFFs 
// output active high global reset sync with two DFFs 
`timescale 1 ns/100 ps
`timescale 1 ns/100 ps
module vl_sync_rst ( rst_n_i, rst_o, clk);
module vl_sync_rst ( rst_n_i, rst_o, clk);
input rst_n_i, clk;
input rst_n_i, clk;
output rst_o;
output rst_o;
reg [0:1] tmp;
reg [0:1] tmp;
always @ (posedge clk or negedge rst_n_i)
always @ (posedge clk or negedge rst_n_i)
if (!rst_n_i)
if (!rst_n_i)
        tmp <= 2'b00;
        tmp <= 2'b00;
else
else
        tmp <= {1'b1,tmp[0]};
        tmp <= {1'b1,tmp[0]};
vl_gbuf buf_i0( .i(tmp[1]), .o(rst_o));
vl_gbuf buf_i0( .i(tmp[1]), .o(rst_o));
endmodule
endmodule
// vl_pll
// vl_pll
`timescale 1 ns/100 ps
`timescale 1 ns/100 ps
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
parameter index = 0;
parameter index = 0;
parameter number_of_clk = 1;
parameter number_of_clk = 1;
parameter period_time_0 = 20;
parameter period_time_0 = 20;
parameter period_time_1 = 20;
parameter period_time_1 = 20;
parameter period_time_2 = 20;
parameter period_time_2 = 20;
parameter lock_delay = 2000;
parameter lock_delay = 2000;
input clk_i, rst_n_i;
input clk_i, rst_n_i;
output lock;
output lock;
output reg [0:number_of_clk-1] clk_o;
output reg [0:number_of_clk-1] clk_o;
output [0:number_of_clk-1] rst_o;
output [0:number_of_clk-1] rst_o;
`ifdef SIM_PLL
`ifdef SIM_PLL
always
always
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
generate if (number_of_clk > 1)
generate if (number_of_clk > 1)
always
always
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
endgenerate
endgenerate
generate if (number_of_clk > 2)
generate if (number_of_clk > 2)
always
always
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
endgenerate
endgenerate
genvar i;
genvar i;
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
end
end
endgenerate
endgenerate
assign #lock_delay lock = rst_n_i;
assign #lock_delay lock = rst_n_i;
endmodule
endmodule
`else
`else
generate if (number_of_clk==1 & index==0) begin
generate if (number_of_clk==1 & index==0) begin
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
end
end
endgenerate // index==0
endgenerate // index==0
generate if (number_of_clk==1 & index==1) begin
generate if (number_of_clk==1 & index==1) begin
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
end
end
endgenerate // index==1
endgenerate // index==1
generate if (number_of_clk==1 & index==2) begin
generate if (number_of_clk==1 & index==2) begin
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
end
end
endgenerate // index==2
endgenerate // index==2
generate if (number_of_clk==1 & index==3) begin
generate if (number_of_clk==1 & index==3) begin
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
end
end
endgenerate // index==0
endgenerate // index==0
generate if (number_of_clk==2 & index==0) begin
generate if (number_of_clk==2 & index==0) begin
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
end
end
endgenerate // index==0
endgenerate // index==0
generate if (number_of_clk==2 & index==1) begin
generate if (number_of_clk==2 & index==1) begin
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
end
end
endgenerate // index==1
endgenerate // index==1
generate if (number_of_clk==2 & index==2) begin
generate if (number_of_clk==2 & index==2) begin
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
end
end
endgenerate // index==2
endgenerate // index==2
generate if (number_of_clk==2 & index==3) begin
generate if (number_of_clk==2 & index==3) begin
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
end
end
endgenerate // index==0
endgenerate // index==0
generate if (number_of_clk==3 & index==0) begin
generate if (number_of_clk==3 & index==0) begin
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
end
end
endgenerate // index==0
endgenerate // index==0
generate if (number_of_clk==3 & index==1) begin
generate if (number_of_clk==3 & index==1) begin
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
end
end
endgenerate // index==1
endgenerate // index==1
generate if (number_of_clk==3 & index==2) begin
generate if (number_of_clk==3 & index==2) begin
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
end
end
endgenerate // index==2
endgenerate // index==2
generate if (number_of_clk==3 & index==3) begin
generate if (number_of_clk==3 & index==3) begin
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
end
end
endgenerate // index==0
endgenerate // index==0
genvar i;
genvar i;
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
end
end
endgenerate
endgenerate
endmodule
endmodule
`endif
`endif
 //actel
 //actel
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile library, registers                                ////
////  Versatile library, registers                                ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Different type of registers                                 ////
////  Different type of registers                                 ////
////                                                              ////
////                                                              ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add more different registers                             ////
////   - add more different registers                             ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
module dff ( d, q, clk, rst);
module dff ( d, q, clk, rst);
        parameter width = 1;
        parameter width = 1;
        parameter reset_value = 0;
        parameter reset_value = 0;
        input [width-1:0] d;
        input [width-1:0] d;
        input clk, rst;
        input clk, rst;
        output reg [width-1:0] q;
        output reg [width-1:0] q;
        always @ (posedge clk or posedge rst)
        always @ (posedge clk or posedge rst)
        if (rst)
        if (rst)
                q <= reset_value;
                q <= reset_value;
        else
        else
                q <= d;
                q <= d;
endmodule
endmodule
module dff_array ( d, q, clk, rst);
module dff_array ( d, q, clk, rst);
        parameter width = 1;
        parameter width = 1;
        parameter depth = 2;
        parameter depth = 2;
        parameter reset_value = 1'b0;
        parameter reset_value = 1'b0;
        input [width-1:0] d;
        input [width-1:0] d;
        input clk, rst;
        input clk, rst;
        output [width-1:0] q;
        output [width-1:0] q;
        reg  [0:depth-1] q_tmp [width-1:0];
        reg  [0:depth-1] q_tmp [width-1:0];
        integer i;
        integer i;
        always @ (posedge clk or posedge rst)
        always @ (posedge clk or posedge rst)
        if (rst) begin
        if (rst) begin
            for (i=0;i<depth;i=i+1)
            for (i=0;i<depth;i=i+1)
                q_tmp[i] <= {width{reset_value}};
                q_tmp[i] <= {width{reset_value}};
        end else begin
        end else begin
            q_tmp[0] <= d;
            q_tmp[0] <= d;
            for (i=1;i<depth;i=i+1)
            for (i=1;i<depth;i=i+1)
                q_tmp[i] <= q_tmp[i-1];
                q_tmp[i] <= q_tmp[i-1];
        end
        end
    assign q = q_tmp[depth-1];
    assign q = q_tmp[depth-1];
endmodule
endmodule
module dff_ce ( d, ce, q, clk, rst);
module dff_ce ( d, ce, q, clk, rst);
        parameter width = 1;
        parameter width = 1;
        parameter reset_value = 0;
        parameter reset_value = 0;
        input [width-1:0] d;
        input [width-1:0] d;
        input ce, clk, rst;
        input ce, clk, rst;
        output reg [width-1:0] q;
        output reg [width-1:0] q;
        always @ (posedge clk or posedge rst)
        always @ (posedge clk or posedge rst)
        if (rst)
        if (rst)
                q <= reset_value;
                q <= reset_value;
        else
        else
                if (ce)
                if (ce)
                        q <= d;
                        q <= d;
endmodule
endmodule
module dff_sr ( aclr, aset, clock, data, q);
module dff_sr ( aclr, aset, clock, data, q);
    input         aclr;
    input         aclr;
    input         aset;
    input         aset;
    input         clock;
    input         clock;
    input         data;
    input         data;
    output reg    q;
    output reg    q;
   always @ (posedge clock or posedge aclr or posedge aset)
   always @ (posedge clock or posedge aclr or posedge aset)
     if (aclr)
     if (aclr)
       q <= 1'b0;
       q <= 1'b0;
     else if (aset)
     else if (aset)
       q <= 1'b1;
       q <= 1'b1;
     else
     else
       q <= data;
       q <= data;
endmodule
endmodule
// LATCH
// LATCH
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
module latch ( d, le, q, clk);
module latch ( d, le, q, clk);
input d, le;
input d, le;
output q;
output q;
input clk;/*
input clk;/*
   always @ (posedge direction_set or posedge direction_clr)
   always @ (posedge direction_set or posedge direction_clr)
     if (direction_clr)
     if (direction_clr)
       direction <= going_empty;
       direction <= going_empty;
     else
     else
       direction <= going_full;*/
       direction <= going_full;*/
endmodule
endmodule
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////  counter                                                     ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// binary counter
// binary counter
module cnt_bin_ce ( cke, q, rst, clk);
module cnt_bin_ce ( cke, q, rst, clk);
   parameter length = 4;
   parameter length = 4;
   input cke;
   input cke;
   output [length:1] q;
   output [length:1] q;
   input rst;
   input rst;
   input clk;
   input clk;
   parameter clear_value = 0;
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter set_value = 1;
   parameter wrap_value = 0;
   parameter wrap_value = 0;
   parameter level1_value = 15;
   parameter level1_value = 15;
   reg  [length:1] qi;
   reg  [length:1] qi;
   wire [length:1] q_next;
   wire [length:1] q_next;
   assign q_next = qi + {{length-1{1'b0}},1'b1};
   assign q_next = qi + {{length-1{1'b0}},1'b1};
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       qi <= {length{1'b0}};
       qi <= {length{1'b0}};
     else
     else
     if (cke)
     if (cke)
       qi <= q_next;
       qi <= q_next;
   assign q = qi;
   assign q = qi;
endmodule
endmodule
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////  counter                                                     ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// binary counter
// binary counter
module cnt_bin_ce_clear ( clear, cke, q, rst, clk);
module cnt_bin_ce_clear ( clear, cke, q, rst, clk);
   parameter length = 4;
   parameter length = 4;
   input clear;
   input clear;
   input cke;
   input cke;
   output [length:1] q;
   output [length:1] q;
   input rst;
   input rst;
   input clk;
   input clk;
   parameter clear_value = 0;
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter set_value = 1;
   parameter wrap_value = 0;
   parameter wrap_value = 0;
   parameter level1_value = 15;
   parameter level1_value = 15;
   reg  [length:1] qi;
   reg  [length:1] qi;
   wire [length:1] q_next;
   wire [length:1] q_next;
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       qi <= {length{1'b0}};
       qi <= {length{1'b0}};
     else
     else
     if (cke)
     if (cke)
       qi <= q_next;
       qi <= q_next;
   assign q = qi;
   assign q = qi;
endmodule
endmodule
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////  counter                                                     ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// binary counter
// binary counter
module cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
module cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
   parameter length = 4;
   parameter length = 4;
   input clear;
   input clear;
   input set;
   input set;
   input cke;
   input cke;
   input rew;
   input rew;
   output [length:1] q;
   output [length:1] q;
   input rst;
   input rst;
   input clk;
   input clk;
   parameter clear_value = 0;
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter set_value = 1;
   parameter wrap_value = 0;
   parameter wrap_value = 0;
   parameter level1_value = 15;
   parameter level1_value = 15;
   reg  [length:1] qi;
   reg  [length:1] qi;
   wire  [length:1] q_next, q_next_fw, q_next_rew;
   wire  [length:1] q_next, q_next_fw, q_next_rew;
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
   assign q_next = rew ? q_next_rew : q_next_fw;
   assign q_next = rew ? q_next_rew : q_next_fw;
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       qi <= {length{1'b0}};
       qi <= {length{1'b0}};
     else
     else
     if (cke)
     if (cke)
       qi <= q_next;
       qi <= q_next;
   assign q = qi;
   assign q = qi;
endmodule
endmodule
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////  counter                                                     ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// binary counter
// binary counter
module cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
module cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
   parameter length = 4;
   parameter length = 4;
   input cke;
   input cke;
   input rew;
   input rew;
   output reg level1;
   output reg level1;
   input rst;
   input rst;
   input clk;
   input clk;
   parameter clear_value = 0;
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter set_value = 1;
   parameter wrap_value = 1;
   parameter wrap_value = 1;
   parameter level1_value = 15;
   parameter level1_value = 15;
   reg  [length:1] qi;
   reg  [length:1] qi;
   wire  [length:1] q_next, q_next_fw, q_next_rew;
   wire  [length:1] q_next, q_next_fw, q_next_rew;
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
   assign q_next = rew ? q_next_rew : q_next_fw;
   assign q_next = rew ? q_next_rew : q_next_fw;
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       qi <= {length{1'b0}};
       qi <= {length{1'b0}};
     else
     else
     if (cke)
     if (cke)
       qi <= q_next;
       qi <= q_next;
    always @ (posedge clk or posedge rst)
    always @ (posedge clk or posedge rst)
    if (rst)
    if (rst)
        level1 <= 1'b0;
        level1 <= 1'b0;
    else
    else
    if (cke)
    if (cke)
    if (q_next == level1_value)
    if (q_next == level1_value)
        level1 <= 1'b1;
        level1 <= 1'b1;
    else if (qi == level1_value & rew)
    else if (qi == level1_value & rew)
        level1 <= 1'b0;
        level1 <= 1'b0;
endmodule
endmodule
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////  counter                                                     ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// LFSR counter
// LFSR counter
module cnt_lfsr_zq ( zq, rst, clk);
module cnt_lfsr_zq ( zq, rst, clk);
   parameter length = 4;
   parameter length = 4;
   output reg zq;
   output reg zq;
   input rst;
   input rst;
   input clk;
   input clk;
   parameter clear_value = 0;
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter set_value = 1;
   parameter wrap_value = 8;
   parameter wrap_value = 8;
   parameter level1_value = 15;
   parameter level1_value = 15;
   reg  [length:1] qi;
   reg  [length:1] qi;
   reg lfsr_fb;
   reg lfsr_fb;
   wire [length:1] q_next;
   wire [length:1] q_next;
   reg [32:1] polynom;
   reg [32:1] polynom;
   integer i;
   integer i;
   always @ (qi)
   always @ (qi)
   begin
   begin
        case (length)
        case (length)
         2: polynom = 32'b11;                               // 0x3
         2: polynom = 32'b11;                               // 0x3
         3: polynom = 32'b110;                              // 0x6
         3: polynom = 32'b110;                              // 0x6
         4: polynom = 32'b1100;                             // 0xC
         4: polynom = 32'b1100;                             // 0xC
         5: polynom = 32'b10100;                            // 0x14
         5: polynom = 32'b10100;                            // 0x14
         6: polynom = 32'b110000;                           // 0x30
         6: polynom = 32'b110000;                           // 0x30
         7: polynom = 32'b1100000;                          // 0x60
         7: polynom = 32'b1100000;                          // 0x60
         8: polynom = 32'b10111000;                         // 0xb8
         8: polynom = 32'b10111000;                         // 0xb8
         9: polynom = 32'b100010000;                        // 0x110
         9: polynom = 32'b100010000;                        // 0x110
        10: polynom = 32'b1001000000;                       // 0x240
        10: polynom = 32'b1001000000;                       // 0x240
        11: polynom = 32'b10100000000;                      // 0x500
        11: polynom = 32'b10100000000;                      // 0x500
        12: polynom = 32'b100000101001;                     // 0x829
        12: polynom = 32'b100000101001;                     // 0x829
        13: polynom = 32'b1000000001100;                    // 0x100C
        13: polynom = 32'b1000000001100;                    // 0x100C
        14: polynom = 32'b10000000010101;                   // 0x2015
        14: polynom = 32'b10000000010101;                   // 0x2015
        15: polynom = 32'b110000000000000;                  // 0x6000
        15: polynom = 32'b110000000000000;                  // 0x6000
        16: polynom = 32'b1101000000001000;                 // 0xD008
        16: polynom = 32'b1101000000001000;                 // 0xD008
        17: polynom = 32'b10010000000000000;                // 0x12000
        17: polynom = 32'b10010000000000000;                // 0x12000
        18: polynom = 32'b100000010000000000;               // 0x20400
        18: polynom = 32'b100000010000000000;               // 0x20400
        19: polynom = 32'b1000000000000100011;              // 0x40023
        19: polynom = 32'b1000000000000100011;              // 0x40023
        20: polynom = 32'b10000010000000000000;             // 0x82000
        20: polynom = 32'b10000010000000000000;             // 0x82000
        21: polynom = 32'b101000000000000000000;            // 0x140000
        21: polynom = 32'b101000000000000000000;            // 0x140000
        22: polynom = 32'b1100000000000000000000;           // 0x300000
        22: polynom = 32'b1100000000000000000000;           // 0x300000
        23: polynom = 32'b10000100000000000000000;          // 0x420000
        23: polynom = 32'b10000100000000000000000;          // 0x420000
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
        default: polynom = 32'b0;
        default: polynom = 32'b0;
        endcase
        endcase
        lfsr_fb = qi[length];
        lfsr_fb = qi[length];
        for (i=length-1; i>=1; i=i-1) begin
        for (i=length-1; i>=1; i=i-1) begin
            if (polynom[i])
            if (polynom[i])
                lfsr_fb = lfsr_fb  ~^ qi[i];
                lfsr_fb = lfsr_fb  ~^ qi[i];
        end
        end
    end
    end
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       qi <= {length{1'b0}};
       qi <= {length{1'b0}};
     else
     else
       qi <= q_next;
       qi <= q_next;
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       zq <= 1'b1;
       zq <= 1'b1;
     else
     else
       zq <= q_next == {length{1'b0}};
       zq <= q_next == {length{1'b0}};
endmodule
endmodule
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////  counter                                                     ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// LFSR counter
// LFSR counter
module cnt_lfsr_ce_zq ( cke, zq, rst, clk);
module cnt_lfsr_ce_zq ( cke, zq, rst, clk);
   parameter length = 4;
   parameter length = 4;
   input cke;
   input cke;
   output reg zq;
   output reg zq;
   input rst;
   input rst;
   input clk;
   input clk;
   parameter clear_value = 0;
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter set_value = 1;
   parameter wrap_value = 8;
   parameter wrap_value = 8;
   parameter level1_value = 15;
   parameter level1_value = 15;
   reg  [length:1] qi;
   reg  [length:1] qi;
   reg lfsr_fb;
   reg lfsr_fb;
   wire [length:1] q_next;
   wire [length:1] q_next;
   reg [32:1] polynom;
   reg [32:1] polynom;
   integer i;
   integer i;
   always @ (qi)
   always @ (qi)
   begin
   begin
        case (length)
        case (length)
         2: polynom = 32'b11;                               // 0x3
         2: polynom = 32'b11;                               // 0x3
         3: polynom = 32'b110;                              // 0x6
         3: polynom = 32'b110;                              // 0x6
         4: polynom = 32'b1100;                             // 0xC
         4: polynom = 32'b1100;                             // 0xC
         5: polynom = 32'b10100;                            // 0x14
         5: polynom = 32'b10100;                            // 0x14
         6: polynom = 32'b110000;                           // 0x30
         6: polynom = 32'b110000;                           // 0x30
         7: polynom = 32'b1100000;                          // 0x60
         7: polynom = 32'b1100000;                          // 0x60
         8: polynom = 32'b10111000;                         // 0xb8
         8: polynom = 32'b10111000;                         // 0xb8
         9: polynom = 32'b100010000;                        // 0x110
         9: polynom = 32'b100010000;                        // 0x110
        10: polynom = 32'b1001000000;                       // 0x240
        10: polynom = 32'b1001000000;                       // 0x240
        11: polynom = 32'b10100000000;                      // 0x500
        11: polynom = 32'b10100000000;                      // 0x500
        12: polynom = 32'b100000101001;                     // 0x829
        12: polynom = 32'b100000101001;                     // 0x829
        13: polynom = 32'b1000000001100;                    // 0x100C
        13: polynom = 32'b1000000001100;                    // 0x100C
        14: polynom = 32'b10000000010101;                   // 0x2015
        14: polynom = 32'b10000000010101;                   // 0x2015
        15: polynom = 32'b110000000000000;                  // 0x6000
        15: polynom = 32'b110000000000000;                  // 0x6000
        16: polynom = 32'b1101000000001000;                 // 0xD008
        16: polynom = 32'b1101000000001000;                 // 0xD008
        17: polynom = 32'b10010000000000000;                // 0x12000
        17: polynom = 32'b10010000000000000;                // 0x12000
        18: polynom = 32'b100000010000000000;               // 0x20400
        18: polynom = 32'b100000010000000000;               // 0x20400
        19: polynom = 32'b1000000000000100011;              // 0x40023
        19: polynom = 32'b1000000000000100011;              // 0x40023
        20: polynom = 32'b10000010000000000000;             // 0x82000
        20: polynom = 32'b10000010000000000000;             // 0x82000
        21: polynom = 32'b101000000000000000000;            // 0x140000
        21: polynom = 32'b101000000000000000000;            // 0x140000
        22: polynom = 32'b1100000000000000000000;           // 0x300000
        22: polynom = 32'b1100000000000000000000;           // 0x300000
        23: polynom = 32'b10000100000000000000000;          // 0x420000
        23: polynom = 32'b10000100000000000000000;          // 0x420000
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
        default: polynom = 32'b0;
        default: polynom = 32'b0;
        endcase
        endcase
        lfsr_fb = qi[length];
        lfsr_fb = qi[length];
        for (i=length-1; i>=1; i=i-1) begin
        for (i=length-1; i>=1; i=i-1) begin
            if (polynom[i])
            if (polynom[i])
                lfsr_fb = lfsr_fb  ~^ qi[i];
                lfsr_fb = lfsr_fb  ~^ qi[i];
        end
        end
    end
    end
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       qi <= {length{1'b0}};
       qi <= {length{1'b0}};
     else
     else
     if (cke)
     if (cke)
       qi <= q_next;
       qi <= q_next;
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       zq <= 1'b1;
       zq <= 1'b1;
     else
     else
     if (cke)
     if (cke)
       zq <= q_next == {length{1'b0}};
       zq <= q_next == {length{1'b0}};
endmodule
endmodule
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////  counter                                                     ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// LFSR counter
// LFSR counter
module cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
module cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
   parameter length = 4;
   parameter length = 4;
   input cke;
   input cke;
   input rew;
   input rew;
   output reg level1;
   output reg level1;
   input rst;
   input rst;
   input clk;
   input clk;
   parameter clear_value = 0;
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter set_value = 1;
   parameter wrap_value = 8;
   parameter wrap_value = 8;
   parameter level1_value = 15;
   parameter level1_value = 15;
   reg  [length:1] qi;
   reg  [length:1] qi;
   reg lfsr_fb, lfsr_fb_rew;
   reg lfsr_fb, lfsr_fb_rew;
   wire  [length:1] q_next, q_next_fw, q_next_rew;
   wire  [length:1] q_next, q_next_fw, q_next_rew;
   reg [32:1] polynom_rew;
   reg [32:1] polynom_rew;
   integer j;
   integer j;
   reg [32:1] polynom;
   reg [32:1] polynom;
   integer i;
   integer i;
   always @ (qi)
   always @ (qi)
   begin
   begin
        case (length)
        case (length)
         2: polynom = 32'b11;                               // 0x3
         2: polynom = 32'b11;                               // 0x3
         3: polynom = 32'b110;                              // 0x6
         3: polynom = 32'b110;                              // 0x6
         4: polynom = 32'b1100;                             // 0xC
         4: polynom = 32'b1100;                             // 0xC
         5: polynom = 32'b10100;                            // 0x14
         5: polynom = 32'b10100;                            // 0x14
         6: polynom = 32'b110000;                           // 0x30
         6: polynom = 32'b110000;                           // 0x30
         7: polynom = 32'b1100000;                          // 0x60
         7: polynom = 32'b1100000;                          // 0x60
         8: polynom = 32'b10111000;                         // 0xb8
         8: polynom = 32'b10111000;                         // 0xb8
         9: polynom = 32'b100010000;                        // 0x110
         9: polynom = 32'b100010000;                        // 0x110
        10: polynom = 32'b1001000000;                       // 0x240
        10: polynom = 32'b1001000000;                       // 0x240
        11: polynom = 32'b10100000000;                      // 0x500
        11: polynom = 32'b10100000000;                      // 0x500
        12: polynom = 32'b100000101001;                     // 0x829
        12: polynom = 32'b100000101001;                     // 0x829
        13: polynom = 32'b1000000001100;                    // 0x100C
        13: polynom = 32'b1000000001100;                    // 0x100C
        14: polynom = 32'b10000000010101;                   // 0x2015
        14: polynom = 32'b10000000010101;                   // 0x2015
        15: polynom = 32'b110000000000000;                  // 0x6000
        15: polynom = 32'b110000000000000;                  // 0x6000
        16: polynom = 32'b1101000000001000;                 // 0xD008
        16: polynom = 32'b1101000000001000;                 // 0xD008
        17: polynom = 32'b10010000000000000;                // 0x12000
        17: polynom = 32'b10010000000000000;                // 0x12000
        18: polynom = 32'b100000010000000000;               // 0x20400
        18: polynom = 32'b100000010000000000;               // 0x20400
        19: polynom = 32'b1000000000000100011;              // 0x40023
        19: polynom = 32'b1000000000000100011;              // 0x40023
        20: polynom = 32'b10000010000000000000;             // 0x82000
        20: polynom = 32'b10000010000000000000;             // 0x82000
        21: polynom = 32'b101000000000000000000;            // 0x140000
        21: polynom = 32'b101000000000000000000;            // 0x140000
        22: polynom = 32'b1100000000000000000000;           // 0x300000
        22: polynom = 32'b1100000000000000000000;           // 0x300000
        23: polynom = 32'b10000100000000000000000;          // 0x420000
        23: polynom = 32'b10000100000000000000000;          // 0x420000
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
        default: polynom = 32'b0;
        default: polynom = 32'b0;
        endcase
        endcase
        lfsr_fb = qi[length];
        lfsr_fb = qi[length];
        for (i=length-1; i>=1; i=i-1) begin
        for (i=length-1; i>=1; i=i-1) begin
            if (polynom[i])
            if (polynom[i])
                lfsr_fb = lfsr_fb  ~^ qi[i];
                lfsr_fb = lfsr_fb  ~^ qi[i];
        end
        end
    end
    end
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
   always @ (qi)
   always @ (qi)
   begin
   begin
        case (length)
        case (length)
         2: polynom_rew = 32'b11;
         2: polynom_rew = 32'b11;
         3: polynom_rew = 32'b110;
         3: polynom_rew = 32'b110;
         4: polynom_rew = 32'b1100;
         4: polynom_rew = 32'b1100;
         5: polynom_rew = 32'b10100;
         5: polynom_rew = 32'b10100;
         6: polynom_rew = 32'b110000;
         6: polynom_rew = 32'b110000;
         7: polynom_rew = 32'b1100000;
         7: polynom_rew = 32'b1100000;
         8: polynom_rew = 32'b10111000;
         8: polynom_rew = 32'b10111000;
         9: polynom_rew = 32'b100010000;
         9: polynom_rew = 32'b100010000;
        10: polynom_rew = 32'b1001000000;
        10: polynom_rew = 32'b1001000000;
        11: polynom_rew = 32'b10100000000;
        11: polynom_rew = 32'b10100000000;
        12: polynom_rew = 32'b100000101001;
        12: polynom_rew = 32'b100000101001;
        13: polynom_rew = 32'b1000000001100;
        13: polynom_rew = 32'b1000000001100;
        14: polynom_rew = 32'b10000000010101;
        14: polynom_rew = 32'b10000000010101;
        15: polynom_rew = 32'b110000000000000;
        15: polynom_rew = 32'b110000000000000;
        16: polynom_rew = 32'b1101000000001000;
        16: polynom_rew = 32'b1101000000001000;
        17: polynom_rew = 32'b10010000000000000;
        17: polynom_rew = 32'b10010000000000000;
        18: polynom_rew = 32'b100000010000000000;
        18: polynom_rew = 32'b100000010000000000;
        19: polynom_rew = 32'b1000000000000100011;
        19: polynom_rew = 32'b1000000000000100011;
        20: polynom_rew = 32'b10000010000000000000;
        20: polynom_rew = 32'b10000010000000000000;
        21: polynom_rew = 32'b101000000000000000000;
        21: polynom_rew = 32'b101000000000000000000;
        22: polynom_rew = 32'b1100000000000000000000;
        22: polynom_rew = 32'b1100000000000000000000;
        23: polynom_rew = 32'b10000100000000000000000;
        23: polynom_rew = 32'b10000100000000000000000;
        24: polynom_rew = 32'b111000010000000000000000;
        24: polynom_rew = 32'b111000010000000000000000;
        25: polynom_rew = 32'b1001000000000000000000000;
        25: polynom_rew = 32'b1001000000000000000000000;
        26: polynom_rew = 32'b10000000000000000000100011;
        26: polynom_rew = 32'b10000000000000000000100011;
        27: polynom_rew = 32'b100000000000000000000010011;
        27: polynom_rew = 32'b100000000000000000000010011;
        28: polynom_rew = 32'b1100100000000000000000000000;
        28: polynom_rew = 32'b1100100000000000000000000000;
        29: polynom_rew = 32'b10100000000000000000000000000;
        29: polynom_rew = 32'b10100000000000000000000000000;
        30: polynom_rew = 32'b100000000000000000000000101001;
        30: polynom_rew = 32'b100000000000000000000000101001;
        31: polynom_rew = 32'b1001000000000000000000000000000;
        31: polynom_rew = 32'b1001000000000000000000000000000;
        32: polynom_rew = 32'b10000000001000000000000000000011;
        32: polynom_rew = 32'b10000000001000000000000000000011;
        default: polynom_rew = 32'b0;
        default: polynom_rew = 32'b0;
        endcase
        endcase
        // rotate left
        // rotate left
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
        lfsr_fb_rew = qi[length];
        lfsr_fb_rew = qi[length];
        for (i=length-1; i>=1; i=i-1) begin
        for (i=length-1; i>=1; i=i-1) begin
            if (polynom_rew[i])
            if (polynom_rew[i])
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
        end
        end
    end
    end
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
   assign q_next = rew ? q_next_rew : q_next_fw;
   assign q_next = rew ? q_next_rew : q_next_fw;
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       qi <= {length{1'b0}};
       qi <= {length{1'b0}};
     else
     else
     if (cke)
     if (cke)
       qi <= q_next;
       qi <= q_next;
    always @ (posedge clk or posedge rst)
    always @ (posedge clk or posedge rst)
    if (rst)
    if (rst)
        level1 <= 1'b0;
        level1 <= 1'b0;
    else
    else
    if (cke)
    if (cke)
    if (q_next == level1_value)
    if (q_next == level1_value)
        level1 <= 1'b1;
        level1 <= 1'b1;
    else if (qi == level1_value & rew)
    else if (qi == level1_value & rew)
        level1 <= 1'b0;
        level1 <= 1'b0;
endmodule
endmodule
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////  counter                                                     ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// GRAY counter
// GRAY counter
module cnt_gray ( q, rst, clk);
module cnt_gray ( q, rst, clk);
   parameter length = 4;
   parameter length = 4;
   output reg [length:1] q;
   output reg [length:1] q;
   input rst;
   input rst;
   input clk;
   input clk;
   parameter clear_value = 0;
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter set_value = 1;
   parameter wrap_value = 8;
   parameter wrap_value = 8;
   parameter level1_value = 15;
   parameter level1_value = 15;
   reg  [length:1] qi;
   reg  [length:1] qi;
   wire [length:1] q_next;
   wire [length:1] q_next;
   assign q_next = qi + {{length-1{1'b0}},1'b1};
   assign q_next = qi + {{length-1{1'b0}},1'b1};
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       qi <= {length{1'b0}};
       qi <= {length{1'b0}};
     else
     else
       qi <= q_next;
       qi <= q_next;
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       q <= {length{1'b0}};
       q <= {length{1'b0}};
     else
     else
         q <= (q_next>>1) ^ q_next;
         q <= (q_next>>1) ^ q_next;
endmodule
endmodule
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////  counter                                                     ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// GRAY counter
// GRAY counter
module cnt_gray_ce ( cke, q, rst, clk);
module cnt_gray_ce ( cke, q, rst, clk);
   parameter length = 4;
   parameter length = 4;
   input cke;
   input cke;
   output reg [length:1] q;
   output reg [length:1] q;
   input rst;
   input rst;
   input clk;
   input clk;
   parameter clear_value = 0;
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter set_value = 1;
   parameter wrap_value = 8;
   parameter wrap_value = 8;
   parameter level1_value = 15;
   parameter level1_value = 15;
   reg  [length:1] qi;
   reg  [length:1] qi;
   wire [length:1] q_next;
   wire [length:1] q_next;
   assign q_next = qi + {{length-1{1'b0}},1'b1};
   assign q_next = qi + {{length-1{1'b0}},1'b1};
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       qi <= {length{1'b0}};
       qi <= {length{1'b0}};
     else
     else
     if (cke)
     if (cke)
       qi <= q_next;
       qi <= q_next;
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       q <= {length{1'b0}};
       q <= {length{1'b0}};
     else
     else
       if (cke)
       if (cke)
         q <= (q_next>>1) ^ q_next;
         q <= (q_next>>1) ^ q_next;
endmodule
endmodule
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile counter                                           ////
////  Versatile counter                                           ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
////  counter                                                     ////
////  counter                                                     ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add LFSR with more taps                                  ////
////   - add LFSR with more taps                                  ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// GRAY counter
// GRAY counter
module cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
module cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
   parameter length = 4;
   parameter length = 4;
   input cke;
   input cke;
   output reg [length:1] q;
   output reg [length:1] q;
   output [length:1] q_bin;
   output [length:1] q_bin;
   input rst;
   input rst;
   input clk;
   input clk;
   parameter clear_value = 0;
   parameter clear_value = 0;
   parameter set_value = 1;
   parameter set_value = 1;
   parameter wrap_value = 8;
   parameter wrap_value = 8;
   parameter level1_value = 15;
   parameter level1_value = 15;
   reg  [length:1] qi;
   reg  [length:1] qi;
   wire [length:1] q_next;
   wire [length:1] q_next;
   assign q_next = qi + {{length-1{1'b0}},1'b1};
   assign q_next = qi + {{length-1{1'b0}},1'b1};
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       qi <= {length{1'b0}};
       qi <= {length{1'b0}};
     else
     else
     if (cke)
     if (cke)
       qi <= q_next;
       qi <= q_next;
   always @ (posedge clk or posedge rst)
   always @ (posedge clk or posedge rst)
     if (rst)
     if (rst)
       q <= {length{1'b0}};
       q <= {length{1'b0}};
     else
     else
       if (cke)
       if (cke)
         q <= (q_next>>1) ^ q_next;
         q <= (q_next>>1) ^ q_next;
   assign q_bin = qi;
   assign q_bin = qi;
endmodule
endmodule
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile library, counters                                 ////
////  Versatile library, counters                                 ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  counters                                                    ////
////  counters                                                    ////
////                                                              ////
////                                                              ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add more counters                                        ////
////   - add more counters                                        ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
module cnt_shreg_wrap ( q, rst, clk);
module cnt_shreg_wrap ( q, rst, clk);
   parameter length = 4;
   parameter length = 4;
   output reg [0:length-1] q;
   output reg [0:length-1] q;
   input rst;
   input rst;
   input clk;
   input clk;
    always @ (posedge clk or posedge rst)
    always @ (posedge clk or posedge rst)
    if (rst)
    if (rst)
        q <= {1'b1,{length-1{1'b0}}};
        q <= {1'b1,{length-1{1'b0}}};
    else
    else
        q <= {q[length-1],q[0:length-2]};
        q <= {q[length-1],q[0:length-2]};
endmodule
endmodule
module cnt_shreg_ce_wrap ( cke, q, rst, clk);
module cnt_shreg_ce_wrap ( cke, q, rst, clk);
   parameter length = 4;
   parameter length = 4;
   input cke;
   input cke;
   output reg [0:length-1] q;
   output reg [0:length-1] q;
   input rst;
   input rst;
   input clk;
   input clk;
    always @ (posedge clk or posedge rst)
    always @ (posedge clk or posedge rst)
    if (rst)
    if (rst)
        q <= {1'b1,{length-1{1'b0}}};
        q <= {1'b1,{length-1{1'b0}}};
    else
    else
        if (cke)
        if (cke)
            q <= {q[length-1],q[0:length-2]};
            q <= {q[length-1],q[0:length-2]};
endmodule
endmodule
module cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
module cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
   parameter length = 4;
   parameter length = 4;
   input cke, clear;
   input cke, clear;
   output reg [0:length-1] q;
   output reg [0:length-1] q;
   input rst;
   input rst;
   input clk;
   input clk;
    always @ (posedge clk or posedge rst)
    always @ (posedge clk or posedge rst)
    if (rst)
    if (rst)
        q <= {1'b1,{length-1{1'b0}}};
        q <= {1'b1,{length-1{1'b0}}};
    else
    else
        if (cke)
        if (cke)
            if (clear)
            if (clear)
                q <= {1'b1,{length-1{1'b0}}};
                q <= {1'b1,{length-1{1'b0}}};
            else
            else
                q <= q >> 1;
                q <= q >> 1;
endmodule
endmodule
module cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
module cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
   parameter length = 4;
   parameter length = 4;
   input cke, clear;
   input cke, clear;
   output reg [0:length-1] q;
   output reg [0:length-1] q;
   input rst;
   input rst;
   input clk;
   input clk;
    always @ (posedge clk or posedge rst)
    always @ (posedge clk or posedge rst)
    if (rst)
    if (rst)
        q <= {1'b1,{length-1{1'b0}}};
        q <= {1'b1,{length-1{1'b0}}};
    else
    else
        if (cke)
        if (cke)
            if (clear)
            if (clear)
                q <= {1'b1,{length-1{1'b0}}};
                q <= {1'b1,{length-1{1'b0}}};
            else
            else
            q <= {q[length-1],q[0:length-2]};
            q <= {q[length-1],q[0:length-2]};
endmodule
endmodule
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  Versatile library, memories                                 ////
////  Versatile library, memories                                 ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////  memories                                                    ////
////  memories                                                    ////
////                                                              ////
////                                                              ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   - add more memory types                                    ////
////   - add more memory types                                    ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB                                              ////
////        ORSoC AB                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
//// later version.                                               ////
////                                                              ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
//// details.                                                     ////
////                                                              ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
/// ROM
/// ROM
module vl_rom ( a, q, clk);
module vl_rom_init ( adr, q, clk);
 
   parameter data_width = 32;
 
   parameter addr_width = 8;
 
   input [(addr_width-1):0]       adr;
 
   output reg [(data_width-1):0] q;
 
   input                         clk;
 
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
 
   parameter memory_file = "vl_rom.vmem";
 
   initial
 
     begin
 
        $readmemh(memory_file, rom);
 
     end
 
   always @ (posedge clk)
 
     q <= rom[adr];
 
endmodule
 
module vl_rom ( adr, q, clk);
parameter data_width = 32;
parameter data_width = 32;
parameter addr_width = 4;
parameter addr_width = 4;
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
    {32'h18000000},
    {32'h18000000},
    {32'hA8200000},
    {32'hA8200000},
    {32'hA8200000},
    {32'hA8200000},
    {32'hA8200000},
    {32'hA8200000},
    {32'h44003000},
    {32'h44003000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000},
    {32'h15000000}};
    {32'h15000000}};
input [addr_width-1:0] a;
input [addr_width-1:0] adr;
output reg [data_width-1:0] q;
output reg [data_width-1:0] q;
input clk;
input clk;
always @ (posedge clk)
always @ (posedge clk)
    q <= data[a];
    q <= data[adr];
endmodule
endmodule
// Single port RAM
// Single port RAM
module vl_ram ( d, adr, we, q, clk);
module vl_ram ( d, adr, we, q, clk);
   parameter data_width = 32;
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter addr_width = 8;
   input [(data_width-1):0]      d;
   input [(data_width-1):0]      d;
   input [(addr_width-1):0]       adr;
   input [(addr_width-1):0]       adr;
   input                         we;
   input                         we;
   output reg [(data_width-1):0]          q;
   output reg [(data_width-1):0] q;
   input                         clk;
   input                         clk;
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
 
   parameter init = 0;
 
   parameter memory_file = "vl_ram.vmem";
 
   generate if (init) begin : init_mem
 
   initial
 
     begin
 
        $readmemh(memory_file, ram);
 
     end
 
   end
 
   endgenerate
   always @ (posedge clk)
   always @ (posedge clk)
   begin
   begin
   if (we)
   if (we)
     ram[adr] <= d;
     ram[adr] <= d;
   q <= ram[adr];
   q <= ram[adr];
   end
   end
endmodule
endmodule
 
module vl_ram_be ( d, adr, be, we, q, clk);
 
   parameter data_width = 32;
 
   parameter addr_width = 8;
 
   input [(data_width-1):0]      d;
 
   input [(addr_width-1):0]       adr;
 
   input [(addr_width/4)-1:0]    be;
 
   input                         we;
 
   output reg [(data_width-1):0] q;
 
   input                         clk;
 
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
 
   parameter init = 0;
 
   parameter memory_file = "vl_ram.vmem";
 
   generate if (init) begin : init_mem
 
   initial
 
     begin
 
        $readmemh(memory_file, ram);
 
     end
 
   end
 
   endgenerate
 
   genvar i;
 
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
 
      always @ (posedge clk)
 
      if (we & be[i])
 
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
 
   end
 
   endgenerate
 
   always @ (posedge clk)
 
      q <= ram[adr];
 
endmodule
// Dual port RAM
// Dual port RAM
// ACTEL FPGA should not use logic to handle rw collision
// ACTEL FPGA should not use logic to handle rw collision
module vl_dual_port_ram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
   parameter data_width = 32;
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter addr_width = 8;
   input [(data_width-1):0]      d_a;
   input [(data_width-1):0]      d_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_b;
   input [(addr_width-1):0]       adr_b;
   input                         we_a;
   input                         we_a;
   output [(data_width-1):0]      q_b;
   output [(data_width-1):0]      q_b;
   input                         clk_a, clk_b;
   input                         clk_a, clk_b;
   reg [(addr_width-1):0]         adr_b_reg;
   reg [(addr_width-1):0]         adr_b_reg;
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
 
   parameter init = 0;
 
   parameter memory_file = "vl_ram.vmem";
 
   generate if (init) begin : init_mem
 
   initial
 
     begin
 
        $readmemh(memory_file, ram);
 
     end
 
   end
 
   endgenerate
   always @ (posedge clk_a)
   always @ (posedge clk_a)
   if (we_a)
   if (we_a)
     ram[adr_a] <= d_a;
     ram[adr_a] <= d_a;
   always @ (posedge clk_b)
   always @ (posedge clk_b)
   adr_b_reg <= adr_b;
   adr_b_reg <= adr_b;
   assign q_b = ram[adr_b_reg];
   assign q_b = ram[adr_b_reg];
endmodule
endmodule
module vl_dual_port_ram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
   parameter data_width = 32;
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter addr_width = 8;
   input [(data_width-1):0]      d_a;
   input [(data_width-1):0]      d_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_b;
   input [(addr_width-1):0]       adr_b;
   input                         we_a;
   input                         we_a;
   output [(data_width-1):0]      q_b;
   output [(data_width-1):0]      q_b;
   output reg [(data_width-1):0] q_a;
   output reg [(data_width-1):0] q_a;
   input                         clk_a, clk_b;
   input                         clk_a, clk_b;
   reg [(data_width-1):0]         q_b;
   reg [(data_width-1):0]         q_b;
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
 
   parameter init = 0;
 
   parameter memory_file = "vl_ram.vmem";
 
   generate if (init) begin : init_mem
 
   initial
 
     begin
 
        $readmemh(memory_file, ram);
 
     end
 
   end
 
   endgenerate
   always @ (posedge clk_a)
   always @ (posedge clk_a)
     begin
     begin
        q_a <= ram[adr_a];
        q_a <= ram[adr_a];
        if (we_a)
        if (we_a)
             ram[adr_a] <= d_a;
             ram[adr_a] <= d_a;
     end
     end
   always @ (posedge clk_b)
   always @ (posedge clk_b)
          q_b <= ram[adr_b];
          q_b <= ram[adr_b];
endmodule
endmodule
module vl_dual_port_ram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, d_b, we_b, clk_b );
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
   parameter data_width = 32;
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter addr_width = 8;
   input [(data_width-1):0]      d_a;
   input [(data_width-1):0]      d_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_b;
   input [(addr_width-1):0]       adr_b;
   input                         we_a;
   input                         we_a;
   output [(data_width-1):0]      q_b;
   output [(data_width-1):0]      q_b;
   input [(data_width-1):0]       d_b;
   input [(data_width-1):0]       d_b;
   output reg [(data_width-1):0] q_a;
   output reg [(data_width-1):0] q_a;
   input                         we_b;
   input                         we_b;
   input                         clk_a, clk_b;
   input                         clk_a, clk_b;
   reg [(data_width-1):0]         q_b;
   reg [(data_width-1):0]         q_b;
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
 
   parameter init = 0;
 
   parameter memory_file = "vl_ram.vmem";
 
   generate if (init) begin : init_mem
 
   initial
 
     begin
 
        $readmemh(memory_file, ram);
 
     end
 
   end
 
   endgenerate
   always @ (posedge clk_a)
   always @ (posedge clk_a)
     begin
     begin
        q_a <= ram[adr_a];
        q_a <= ram[adr_a];
        if (we_a)
        if (we_a)
             ram[adr_a] <= d_a;
             ram[adr_a] <= d_a;
     end
     end
   always @ (posedge clk_b)
   always @ (posedge clk_b)
     begin
     begin
        q_b <= ram[adr_b];
        q_b <= ram[adr_b];
        if (we_b)
        if (we_b)
          ram[adr_b] <= d_b;
          ram[adr_b] <= d_b;
     end
     end
endmodule
endmodule
// Content addresable memory, CAM
// Content addresable memory, CAM
// FIFO
// FIFO
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
   parameter ADDR_WIDTH = 4;
   parameter ADDR_WIDTH = 4;
   parameter N = ADDR_WIDTH-1;
   parameter N = ADDR_WIDTH-1;
   parameter Q1 = 2'b00;
   parameter Q1 = 2'b00;
   parameter Q2 = 2'b01;
   parameter Q2 = 2'b01;
   parameter Q3 = 2'b11;
   parameter Q3 = 2'b11;
   parameter Q4 = 2'b10;
   parameter Q4 = 2'b10;
   parameter going_empty = 1'b0;
   parameter going_empty = 1'b0;
   parameter going_full  = 1'b1;
   parameter going_full  = 1'b1;
   input [N:0]  wptr, rptr;
   input [N:0]  wptr, rptr;
   output reg   fifo_empty;
   output reg   fifo_empty;
   output       fifo_full;
   output       fifo_full;
   input        wclk, rclk, rst;
   input        wclk, rclk, rst;
   wire direction;
   wire direction;
   reg  direction_set, direction_clr;
   reg  direction_set, direction_clr;
   wire async_empty, async_full;
   wire async_empty, async_full;
   wire fifo_full2;
   wire fifo_full2;
   reg  fifo_empty2;
   reg  fifo_empty2;
   // direction_set
   // direction_set
   always @ (wptr[N:N-1] or rptr[N:N-1])
   always @ (wptr[N:N-1] or rptr[N:N-1])
     case ({wptr[N:N-1],rptr[N:N-1]})
     case ({wptr[N:N-1],rptr[N:N-1]})
       {Q1,Q2} : direction_set <= 1'b1;
       {Q1,Q2} : direction_set <= 1'b1;
       {Q2,Q3} : direction_set <= 1'b1;
       {Q2,Q3} : direction_set <= 1'b1;
       {Q3,Q4} : direction_set <= 1'b1;
       {Q3,Q4} : direction_set <= 1'b1;
       {Q4,Q1} : direction_set <= 1'b1;
       {Q4,Q1} : direction_set <= 1'b1;
       default : direction_set <= 1'b0;
       default : direction_set <= 1'b0;
     endcase
     endcase
   // direction_clear
   // direction_clear
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
     if (rst)
     if (rst)
       direction_clr <= 1'b1;
       direction_clr <= 1'b1;
     else
     else
       case ({wptr[N:N-1],rptr[N:N-1]})
       case ({wptr[N:N-1],rptr[N:N-1]})
         {Q2,Q1} : direction_clr <= 1'b1;
         {Q2,Q1} : direction_clr <= 1'b1;
         {Q3,Q2} : direction_clr <= 1'b1;
         {Q3,Q2} : direction_clr <= 1'b1;
         {Q4,Q3} : direction_clr <= 1'b1;
         {Q4,Q3} : direction_clr <= 1'b1;
         {Q1,Q4} : direction_clr <= 1'b1;
         {Q1,Q4} : direction_clr <= 1'b1;
         default : direction_clr <= 1'b0;
         default : direction_clr <= 1'b0;
       endcase
       endcase
    dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
    dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
   assign async_empty = (wptr == rptr) && (direction==going_empty);
   assign async_empty = (wptr == rptr) && (direction==going_empty);
   assign async_full  = (wptr == rptr) && (direction==going_full);
   assign async_full  = (wptr == rptr) && (direction==going_full);
    dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
    dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
    dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
    dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
/*
/*
   always @ (posedge wclk or posedge rst or posedge async_full)
   always @ (posedge wclk or posedge rst or posedge async_full)
     if (rst)
     if (rst)
       {fifo_full, fifo_full2} <= 2'b00;
       {fifo_full, fifo_full2} <= 2'b00;
     else if (async_full)
     else if (async_full)
       {fifo_full, fifo_full2} <= 2'b11;
       {fifo_full, fifo_full2} <= 2'b11;
     else
     else
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
*/
*/
   always @ (posedge rclk or posedge async_empty)
   always @ (posedge rclk or posedge async_empty)
     if (async_empty)
     if (async_empty)
       {fifo_empty, fifo_empty2} <= 2'b11;
       {fifo_empty, fifo_empty2} <= 2'b11;
     else
     else
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty};
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty};
endmodule // async_comp
endmodule // async_comp
module vl_fifo_1r1w_async (
module vl_fifo_1r1w_async (
    d, wr, fifo_full, wr_clk, wr_rst,
    d, wr, fifo_full, wr_clk, wr_rst,
    q, rd, fifo_empty, rd_clk, rd_rst
    q, rd, fifo_empty, rd_clk, rd_rst
    );
    );
parameter data_width = 18;
parameter data_width = 18;
parameter addr_width = 4;
parameter addr_width = 4;
// write side
// write side
input  [data_width-1:0] d;
input  [data_width-1:0] d;
input                   wr;
input                   wr;
output                  fifo_full;
output                  fifo_full;
input                   wr_clk;
input                   wr_clk;
input                   wr_rst;
input                   wr_rst;
// read side
// read side
output [data_width-1:0] q;
output [data_width-1:0] q;
input                   rd;
input                   rd;
output                  fifo_empty;
output                  fifo_empty;
input                   rd_clk;
input                   rd_clk;
input                   rd_rst;
input                   rd_rst;
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
vl_fifo_1r1w_async (
vl_fifo_1r1w_async (
    d, wr, fifo_full, wr_clk, wr_rst,
    d, wr, fifo_full, wr_clk, wr_rst,
    q, rd, fifo_empty, rd_clk, rd_rst
    q, rd, fifo_empty, rd_clk, rd_rst
    );
    );
adr_gen
cnt_gray_ce_bin
    # ( .length(addr_width))
    # ( .length(addr_width))
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
adr_gen
cnt_gray_ce_bin
    # (.length(addr_width))
    # (.length(addr_width))
    fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
    fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
vl_dual_port_ram_1r1w
vl_dpram_1r1w
    # (.data_width(data_width), .addr_width(addr_width))
    # (.data_width(data_width), .addr_width(addr_width))
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
vl_fifo_cmp_async
vl_fifo_cmp_async
    # (.addr_width(addr_width))
    # (.addr_width(addr_width))
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
endmodule
endmodule
module vl_fifo_2r2w (
module vl_fifo_2r2w (
    // a side
    // a side
    a_d, a_wr, a_fifo_full,
    a_d, a_wr, a_fifo_full,
    a_q, a_rd, a_fifo_empty,
    a_q, a_rd, a_fifo_empty,
    a_clk, a_rst,
    a_clk, a_rst,
    // b side
    // b side
    b_d, b_wr, b_fifo_full,
    b_d, b_wr, b_fifo_full,
    b_q, b_rd, b_fifo_empty,
    b_q, b_rd, b_fifo_empty,
    b_clk, b_rst
    b_clk, b_rst
    );
    );
parameter data_width = 18;
parameter data_width = 18;
parameter addr_width = 4;
parameter addr_width = 4;
// a side
// a side
input  [data_width-1:0] a_d;
input  [data_width-1:0] a_d;
input                   a_wr;
input                   a_wr;
output                  a_fifo_full;
output                  a_fifo_full;
output [data_width-1:0] a_q;
output [data_width-1:0] a_q;
input                   a_rd;
input                   a_rd;
output                  a_fifo_empty;
output                  a_fifo_empty;
input                   a_clk;
input                   a_clk;
input                   a_rst;
input                   a_rst;
// b side
// b side
input  [data_width-1:0] b_d;
input  [data_width-1:0] b_d;
input                   b_wr;
input                   b_wr;
output                  b_fifo_full;
output                  b_fifo_full;
output [data_width-1:0] b_q;
output [data_width-1:0] b_q;
input                   b_rd;
input                   b_rd;
output                  b_fifo_empty;
output                  b_fifo_empty;
input                   b_clk;
input                   b_clk;
input                   b_rst;
input                   b_rst;
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
vl_fifo_1r1w_async_a (
vl_fifo_1r1w_async_a (
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
    );
    );
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
vl_fifo_1r1w_async_b (
vl_fifo_1r1w_async_b (
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
    );
    );
endmodule
endmodule
module vl_fifo_2r2w_simplex (
module vl_fifo_2r2w_simplex (
    // a side
    // a side
    a_d, a_wr, a_fifo_full,
    a_d, a_wr, a_fifo_full,
    a_q, a_rd, a_fifo_empty,
    a_q, a_rd, a_fifo_empty,
    a_clk, a_rst,
    a_clk, a_rst,
    // b side
    // b side
    b_d, b_wr, b_fifo_full,
    b_d, b_wr, b_fifo_full,
    b_q, b_rd, b_fifo_empty,
    b_q, b_rd, b_fifo_empty,
    b_clk, b_rst
    b_clk, b_rst
    );
    );
parameter data_width = 18;
parameter data_width = 18;
parameter addr_width = 4;
parameter addr_width = 4;
// a side
// a side
input  [data_width-1:0] a_d;
input  [data_width-1:0] a_d;
input                   a_wr;
input                   a_wr;
output                  a_fifo_full;
output                  a_fifo_full;
output [data_width-1:0] a_q;
output [data_width-1:0] a_q;
input                   a_rd;
input                   a_rd;
output                  a_fifo_empty;
output                  a_fifo_empty;
input                   a_clk;
input                   a_clk;
input                   a_rst;
input                   a_rst;
// b side
// b side
input  [data_width-1:0] b_d;
input  [data_width-1:0] b_d;
input                   b_wr;
input                   b_wr;
output                  b_fifo_full;
output                  b_fifo_full;
output [data_width-1:0] b_q;
output [data_width-1:0] b_q;
input                   b_rd;
input                   b_rd;
output                  b_fifo_empty;
output                  b_fifo_empty;
input                   b_clk;
input                   b_clk;
input                   b_rst;
input                   b_rst;
// adr_gen
// adr_gen
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
// dpram
// dpram
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
adr_gen
cnt_gray_ce_bin
    # ( .length(addr_width))
    # ( .length(addr_width))
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
adr_gen
cnt_gray_ce_bin
    # (.length(addr_width))
    # (.length(addr_width))
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
adr_gen
cnt_gray_ce_bin
    # ( .length(addr_width))
    # ( .length(addr_width))
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
adr_gen
cnt_gray_ce_bin
    # (.length(addr_width))
    # (.length(addr_width))
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
// mux read or write adr to DPRAM
// mux read or write adr to DPRAM
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
vfifo_dual_port_ram_dc_dw
vl_dp_ram_2r2w
    # (.data_width(data_width), .addr_width(addr_width+1))
    # (.data_width(data_width), .addr_width(addr_width+1))
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
vl_fifo_async_cmp
vl_fifo_async_cmp
    # (.addr_width(addr_width))
    # (.addr_width(addr_width))
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
versatile_fifo_async_cmp
vl_fifo_async_cmp
    # (.addr_width(addr_width))
    # (.addr_width(addr_width))
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
endmodule
endmodule
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.