Subversion Repositories versatile_library

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

////                                                              ////

////                                                              ////

////  Versatile library, clock and reset                          ////

////  Versatile library, clock and reset                          ////

////                                                              ////

////                                                              ////

////  Description                                                 ////

////  Description                                                 ////

////  Logic related to clock and reset                            ////

////  Logic related to clock and reset                            ////

////                                                              ////

////                                                              ////

////                                                              ////

////                                                              ////

////  To Do:                                                      ////

////  To Do:                                                      ////

////   - add more different registers                             ////

////   - add more different registers                             ////

////                                                              ////

////                                                              ////

////  Author(s):                                                  ////

////  Author(s):                                                  ////

////      - Michael Unneback, unneback@opencores.org              ////

////      - Michael Unneback, unneback@opencores.org              ////

////        ORSoC AB                                              ////

////        ORSoC AB                                              ////

////                                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

////                                                              ////

////                                                              ////

//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////

//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////

////                                                              ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

//// later version.                                               ////

////                                                              ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

//// details.                                                     ////

////                                                              ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

// Global buffer

// Global buffer

// usage:

// usage:

// use to enable global buffers for high fan out signals such as clock and reset

// use to enable global buffers for high fan out signals such as clock and reset

`timescale 1 ns/100 ps

`timescale 1 ns/100 ps

// Version: 8.4 8.4.0.33

// Version: 8.4 8.4.0.33

module gbuf(GL,CLK);

module gbuf(GL,CLK);

output GL;

output GL;

input  CLK;

input  CLK;

    wire GND;

    wire GND;

    GND GND_1_net(.Y(GND));

    GND GND_1_net(.Y(GND));

    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),

    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),

        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;

        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;

endmodule

endmodule

`timescale 1 ns/1 ns

`timescale 1 ns/1 ns

module vl_gbuf ( i, o);

module vl_gbuf ( i, o);

input i;

input i;

output o;

output o;

`ifdef SIM_GBUF

`ifdef SIM_GBUF

assign o=i;

assign o=i;

`else

`else

gbuf gbuf_i0 ( .CLK(i), .GL(o));

gbuf gbuf_i0 ( .CLK(i), .GL(o));

`endif

`endif

endmodule

endmodule

 //ACTEL

 //ACTEL

// sync reset

// sync reset

// input active lo async reset, normally from external reset generetaor and/or switch

// input active lo async reset, normally from external reset generetaor and/or switch

// output active high global reset sync with two DFFs 

// output active high global reset sync with two DFFs 

`timescale 1 ns/100 ps

`timescale 1 ns/100 ps

module vl_sync_rst ( rst_n_i, rst_o, clk);

module vl_sync_rst ( rst_n_i, rst_o, clk);

input rst_n_i, clk;

input rst_n_i, clk;

output rst_o;

output rst_o;

reg [0:1] tmp;

reg [0:1] tmp;

always @ (posedge clk or negedge rst_n_i)

always @ (posedge clk or negedge rst_n_i)

if (!rst_n_i)

if (!rst_n_i)

        tmp <= 2'b00;

        tmp <= 2'b00;

else

else

        tmp <= {1'b1,tmp[0]};

        tmp <= {1'b1,tmp[0]};

vl_gbuf buf_i0( .i(tmp[1]), .o(rst_o));

vl_gbuf buf_i0( .i(tmp[1]), .o(rst_o));

endmodule

endmodule

// vl_pll

// vl_pll

`timescale 1 ns/100 ps

`timescale 1 ns/100 ps

module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);

module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);

parameter index = 0;

parameter index = 0;

parameter number_of_clk = 1;

parameter number_of_clk = 1;

parameter period_time_0 = 20;

parameter period_time_0 = 20;

parameter period_time_1 = 20;

parameter period_time_1 = 20;

parameter period_time_2 = 20;

parameter period_time_2 = 20;

parameter lock_delay = 2000;

parameter lock_delay = 2000;

input clk_i, rst_n_i;

input clk_i, rst_n_i;

output lock;

output lock;

output reg [0:number_of_clk-1] clk_o;

output reg [0:number_of_clk-1] clk_o;

output [0:number_of_clk-1] rst_o;

output [0:number_of_clk-1] rst_o;

`ifdef SIM_PLL

`ifdef SIM_PLL

always

always

     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];

     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];

generate if (number_of_clk > 1)

generate if (number_of_clk > 1)

always

always

     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];

     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];

endgenerate

endgenerate

generate if (number_of_clk > 2)

generate if (number_of_clk > 2)

always

always

     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];

     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];

endgenerate

endgenerate

genvar i;

genvar i;

generate for (i=0;i<number_of_clk;i=i+1) begin: clock

generate for (i=0;i<number_of_clk;i=i+1) begin: clock

     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));

     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));

end

end

endgenerate

endgenerate

assign #lock_delay lock = rst_n_i;

assign #lock_delay lock = rst_n_i;

endmodule

endmodule

`else

`else

generate if (number_of_clk==1 & index==0) begin

generate if (number_of_clk==1 & index==0) begin

        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));

        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));

end

end

endgenerate // index==0

endgenerate // index==0

generate if (number_of_clk==1 & index==1) begin

generate if (number_of_clk==1 & index==1) begin

        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));

        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));

end

end

endgenerate // index==1

endgenerate // index==1

generate if (number_of_clk==1 & index==2) begin

generate if (number_of_clk==1 & index==2) begin

        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));

        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));

end

end

endgenerate // index==2

endgenerate // index==2

generate if (number_of_clk==1 & index==3) begin

generate if (number_of_clk==1 & index==3) begin

        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));

        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));

end

end

endgenerate // index==0

endgenerate // index==0

generate if (number_of_clk==2 & index==0) begin

generate if (number_of_clk==2 & index==0) begin

        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));

        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));

end

end

endgenerate // index==0

endgenerate // index==0

generate if (number_of_clk==2 & index==1) begin

generate if (number_of_clk==2 & index==1) begin

        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));

        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));

end

end

endgenerate // index==1

endgenerate // index==1

generate if (number_of_clk==2 & index==2) begin

generate if (number_of_clk==2 & index==2) begin

        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));

        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));

end

end

endgenerate // index==2

endgenerate // index==2

generate if (number_of_clk==2 & index==3) begin

generate if (number_of_clk==2 & index==3) begin

        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));

        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));

end

end

endgenerate // index==0

endgenerate // index==0

generate if (number_of_clk==3 & index==0) begin

generate if (number_of_clk==3 & index==0) begin

        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));

        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));

end

end

endgenerate // index==0

endgenerate // index==0

generate if (number_of_clk==3 & index==1) begin

generate if (number_of_clk==3 & index==1) begin

        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));

        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));

end

end

endgenerate // index==1

endgenerate // index==1

generate if (number_of_clk==3 & index==2) begin

generate if (number_of_clk==3 & index==2) begin

        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));

        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));

end

end

endgenerate // index==2

endgenerate // index==2

generate if (number_of_clk==3 & index==3) begin

generate if (number_of_clk==3 & index==3) begin

        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));

        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));

end

end

endgenerate // index==0

endgenerate // index==0

genvar i;

genvar i;

generate for (i=0;i<number_of_clk;i=i+1) begin: clock

generate for (i=0;i<number_of_clk;i=i+1) begin: clock

        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));

        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));

end

end

endgenerate

endgenerate

endmodule

endmodule

`endif

`endif

 //actel

 //actel

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

////                                                              ////

////                                                              ////

////  Versatile library, registers                                ////

////  Versatile library, registers                                ////

////                                                              ////

////                                                              ////

////  Description                                                 ////

////  Description                                                 ////

////  Different type of registers                                 ////

////  Different type of registers                                 ////

////                                                              ////

////                                                              ////

////                                                              ////

////                                                              ////

////  To Do:                                                      ////

////  To Do:                                                      ////

////   - add more different registers                             ////

////   - add more different registers                             ////

////                                                              ////

////                                                              ////

////  Author(s):                                                  ////

////  Author(s):                                                  ////

////      - Michael Unneback, unneback@opencores.org              ////

////      - Michael Unneback, unneback@opencores.org              ////

////        ORSoC AB                                              ////

////        ORSoC AB                                              ////

////                                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

////                                                              ////

////                                                              ////

//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////

//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////

////                                                              ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

//// later version.                                               ////

////                                                              ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

//// details.                                                     ////

////                                                              ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

module dff ( d, q, clk, rst);

module dff ( d, q, clk, rst);

        parameter width = 1;

        parameter width = 1;

        parameter reset_value = 0;

        parameter reset_value = 0;

        input [width-1:0] d;

        input [width-1:0] d;

        input clk, rst;

        input clk, rst;

        output reg [width-1:0] q;

        output reg [width-1:0] q;

        always @ (posedge clk or posedge rst)

        always @ (posedge clk or posedge rst)

        if (rst)

        if (rst)

                q <= reset_value;

                q <= reset_value;

        else

        else

                q <= d;

                q <= d;

endmodule

endmodule

module dff_array ( d, q, clk, rst);

module dff_array ( d, q, clk, rst);

        parameter width = 1;

        parameter width = 1;

        parameter depth = 2;

        parameter depth = 2;

        parameter reset_value = 1'b0;

        parameter reset_value = 1'b0;

        input [width-1:0] d;

        input [width-1:0] d;

        input clk, rst;

        input clk, rst;

        output [width-1:0] q;

        output [width-1:0] q;

        reg  [0:depth-1] q_tmp [width-1:0];

        reg  [0:depth-1] q_tmp [width-1:0];

        integer i;

        integer i;

        always @ (posedge clk or posedge rst)

        always @ (posedge clk or posedge rst)

        if (rst) begin

        if (rst) begin

            for (i=0;i<depth;i=i+1)

            for (i=0;i<depth;i=i+1)

                q_tmp[i] <= {width{reset_value}};

                q_tmp[i] <= {width{reset_value}};

        end else begin

        end else begin

            q_tmp[0] <= d;

            q_tmp[0] <= d;

            for (i=1;i<depth;i=i+1)

            for (i=1;i<depth;i=i+1)

                q_tmp[i] <= q_tmp[i-1];

                q_tmp[i] <= q_tmp[i-1];

        end

        end

    assign q = q_tmp[depth-1];

    assign q = q_tmp[depth-1];

endmodule

endmodule

module dff_ce ( d, ce, q, clk, rst);

module dff_ce ( d, ce, q, clk, rst);

        parameter width = 1;

        parameter width = 1;

        parameter reset_value = 0;

        parameter reset_value = 0;

        input [width-1:0] d;

        input [width-1:0] d;

        input ce, clk, rst;

        input ce, clk, rst;

        output reg [width-1:0] q;

        output reg [width-1:0] q;

        always @ (posedge clk or posedge rst)

        always @ (posedge clk or posedge rst)

        if (rst)

        if (rst)

                q <= reset_value;

                q <= reset_value;

        else

        else

                if (ce)

                if (ce)

                        q <= d;

                        q <= d;

endmodule

endmodule

module dff_sr ( aclr, aset, clock, data, q);

module dff_sr ( aclr, aset, clock, data, q);

    input         aclr;

    input         aclr;

    input         aset;

    input         aset;

    input         clock;

    input         clock;

    input         data;

    input         data;

    output reg    q;

    output reg    q;

   always @ (posedge clock or posedge aclr or posedge aset)

   always @ (posedge clock or posedge aclr or posedge aset)

     if (aclr)

     if (aclr)

       q <= 1'b0;

       q <= 1'b0;

     else if (aset)

     else if (aset)

       q <= 1'b1;

       q <= 1'b1;

     else

     else

       q <= data;

       q <= data;

endmodule

endmodule

// LATCH

// LATCH

// For targtes not supporting LATCH use dff_sr with clk=1 and data=1

// For targtes not supporting LATCH use dff_sr with clk=1 and data=1

module latch ( d, le, q, clk);

module latch ( d, le, q, clk);

input d, le;

input d, le;

output q;

output q;

input clk;/*

input clk;/*

   always @ (posedge direction_set or posedge direction_clr)

   always @ (posedge direction_set or posedge direction_clr)

     if (direction_clr)

     if (direction_clr)

       direction <= going_empty;

       direction <= going_empty;

     else

     else

       direction <= going_full;*/

       direction <= going_full;*/

endmodule

endmodule

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

////                                                              ////

////                                                              ////

////  Versatile counter                                           ////

////  Versatile counter                                           ////

////                                                              ////

////                                                              ////

////  Description                                                 ////

////  Description                                                 ////

////  Versatile counter, a reconfigurable binary, gray or LFSR    ////

////  Versatile counter, a reconfigurable binary, gray or LFSR    ////

////  counter                                                     ////

////  counter                                                     ////

////                                                              ////

////                                                              ////

////  To Do:                                                      ////

////  To Do:                                                      ////

////   - add LFSR with more taps                                  ////

////   - add LFSR with more taps                                  ////

////                                                              ////

////                                                              ////

////  Author(s):                                                  ////

////  Author(s):                                                  ////

////      - Michael Unneback, unneback@opencores.org              ////

////      - Michael Unneback, unneback@opencores.org              ////

////        ORSoC AB                                              ////

////        ORSoC AB                                              ////

////                                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

////                                                              ////

////                                                              ////

//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////

//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////

////                                                              ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

//// later version.                                               ////

////                                                              ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

//// details.                                                     ////

////                                                              ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

// binary counter

// binary counter

module cnt_bin_ce ( cke, q, rst, clk);

module cnt_bin_ce ( cke, q, rst, clk);

   parameter length = 4;

   parameter length = 4;

   input cke;

   input cke;

   output [length:1] q;

   output [length:1] q;

   input rst;

   input rst;

   input clk;

   input clk;

   parameter clear_value = 0;

   parameter clear_value = 0;

   parameter set_value = 1;

   parameter set_value = 1;

   parameter wrap_value = 0;

   parameter wrap_value = 0;

   parameter level1_value = 15;

   parameter level1_value = 15;

   reg  [length:1] qi;

   reg  [length:1] qi;

   wire [length:1] q_next;

   wire [length:1] q_next;

   assign q_next = qi + {{length-1{1'b0}},1'b1};

   assign q_next = qi + {{length-1{1'b0}},1'b1};

   always @ (posedge clk or posedge rst)

   always @ (posedge clk or posedge rst)

     if (rst)

     if (rst)

       qi <= {length{1'b0}};

       qi <= {length{1'b0}};

     else

     else

     if (cke)

     if (cke)

       qi <= q_next;

       qi <= q_next;

   assign q = qi;

   assign q = qi;

endmodule

endmodule

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

////                                                              ////

////                                                              ////

////  Versatile counter                                           ////

////  Versatile counter                                           ////

////                                                              ////

////                                                              ////

////  Description                                                 ////

////  Description                                                 ////

////  Versatile counter, a reconfigurable binary, gray or LFSR    ////

////  Versatile counter, a reconfigurable binary, gray or LFSR    ////

////  counter                                                     ////

////  counter                                                     ////

////                                                              ////

////                                                              ////

////  To Do:                                                      ////

////  To Do:                                                      ////

////   - add LFSR with more taps                                  ////

////   - add LFSR with more taps                                  ////

////                                                              ////

////                                                              ////

////  Author(s):                                                  ////

////  Author(s):                                                  ////

////      - Michael Unneback, unneback@opencores.org              ////

////      - Michael Unneback, unneback@opencores.org              ////

////        ORSoC AB                                              ////

////        ORSoC AB                                              ////

////                                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

////                                                              ////

////                                                              ////

//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////

//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////

////                                                              ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

//// later version.                                               ////

////                                                              ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

//// details.                                                     ////

////                                                              ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

// binary counter

// binary counter

module cnt_bin_ce_clear ( clear, cke, q, rst, clk);

module cnt_bin_ce_clear ( clear, cke, q, rst, clk);

   parameter length = 4;

   parameter length = 4;

   input clear;

   input clear;

   input cke;

   input cke;

   output [length:1] q;

   output [length:1] q;

   input rst;

   input rst;

   input clk;

   input clk;

   parameter clear_value = 0;

   parameter clear_value = 0;

   parameter set_value = 1;

   parameter set_value = 1;

   parameter wrap_value = 0;

   parameter wrap_value = 0;

   parameter level1_value = 15;

   parameter level1_value = 15;

   reg  [length:1] qi;

   reg  [length:1] qi;

   wire [length:1] q_next;

   wire [length:1] q_next;

   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};

   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};

   always @ (posedge clk or posedge rst)

   always @ (posedge clk or posedge rst)

     if (rst)

     if (rst)

       qi <= {length{1'b0}};

       qi <= {length{1'b0}};

     else

     else

     if (cke)

     if (cke)

       qi <= q_next;

       qi <= q_next;

   assign q = qi;

   assign q = qi;

endmodule

endmodule

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

////                                                              ////

////                                                              ////

////  Versatile counter                                           ////

////  Versatile counter                                           ////

////                                                              ////

////                                                              ////

////  Description                                                 ////

////  Description                                                 ////

////  Versatile counter, a reconfigurable binary, gray or LFSR    ////

////  Versatile counter, a reconfigurable binary, gray or LFSR    ////

////  counter                                                     ////

////  counter                                                     ////

////                                                              ////

////                                                              ////

////  To Do:                                                      ////

////  To Do:                                                      ////

////   - add LFSR with more taps                                  ////

////   - add LFSR with more taps                                  ////

////                                                              ////

////                                                              ////

////  Author(s):                                                  ////

////  Author(s):                                                  ////

////      - Michael Unneback, unneback@opencores.org              ////

////      - Michael Unneback, unneback@opencores.org              ////

////        ORSoC AB                                              ////

////        ORSoC AB                                              ////

////                                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

////                                                              ////

////                                                              ////

//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////

//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////

////                                                              ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

//// later version.                                               ////

////                                                              ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

//// details.                                                     ////

////                                                              ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

// binary counter

// binary counter

module cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);

module cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);

   parameter length = 4;

   parameter length = 4;

   input clear;

   input clear;

   input set;

   input set;

   input cke;

   input cke;

   input rew;

   input rew;

   output [length:1] q;

   output [length:1] q;

   input rst;

   input rst;

   input clk;

   input clk;

   parameter clear_value = 0;

   parameter clear_value = 0;

   parameter set_value = 1;

   parameter set_value = 1;

   parameter wrap_value = 0;

   parameter wrap_value = 0;

   parameter level1_value = 15;

   parameter level1_value = 15;

   reg  [length:1] qi;

   reg  [length:1] qi;

   wire  [length:1] q_next, q_next_fw, q_next_rew;

   wire  [length:1] q_next, q_next_fw, q_next_rew;

   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};

   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};

   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};

   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};

   assign q_next = rew ? q_next_rew : q_next_fw;

   assign q_next = rew ? q_next_rew : q_next_fw;

   always @ (posedge clk or posedge rst)

   always @ (posedge clk or posedge rst)

     if (rst)

     if (rst)

       qi <= {length{1'b0}};

       qi <= {length{1'b0}};

     else

     else

     if (cke)

     if (cke)

       qi <= q_next;

       qi <= q_next;

   assign q = qi;

   assign q = qi;

endmodule

endmodule