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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Diff between revs 78 and 79

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Rev 78 Rev 79
Line 2145... Line 2145...
input rst;
input rst;
wire [1:0] wbm_bte_o;
wire [1:0] wbm_bte_o;
wire [2:0] wbm_cti_o;
wire [2:0] wbm_cti_o;
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
reg last_cyc;
reg last_cyc;
 
reg [3:0] counter;
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
if (rst)
if (rst)
    last_cyc <= 1'b0;
    last_cyc <= 1'b0;
else
else
    last_cyc <= wbm_cyc_o;
    last_cyc <= wbm_cyc_o;
 
always @ (posedge clk or posedge rst)
 
if (rst)
 
    read <= 1'b0;
 
else
 
    if (!last_cyc & wbm_cyc_o)
 
        read <= 1'b1;
 
    else if (!waitrequest)
 
        read <= 1'b0;
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
                    (wbm_bte_o==2'b10) ? 4'd8 :
                    (wbm_bte_o==2'b10) ? 4'd8 :
                    (wbm_bte_o==2'b11) ? 4'd16:
                    (wbm_bte_o==2'b11) ? 4'd16:
                    4'd1;
                    4'd1;
assign write = wbm_cyc_o & wbm_stb_o &  wbm_we_o;
 
assign read  = wbm_cyc_o & wbm_stb_o & !wbm_we_o;
 
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest);
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest);
 
always @ (posedge clk or posedge rst)
 
if (rst) begin
 
    counter <= 4'd0;
 
    write <= 1'b0;
 
end else
 
    if (!waitrequest & last_cyc & wbm_cyc_o) begin
 
        write <= 1'b1;
 
        counter <= burstcount -1;
 
    end else if (waitrequest & last_cyc & wbm_cyc_o) begin
 
        write <= 1'b1;
 
        counter <= burstcount;
 
    end else if (!waitrequst) begin
 
        counter <= counter - 4'd1;
 
        write <= (counter!=4'd0 & wbm_stb_o)
 
    end
vl_wb3wb3_bridge wbwb3inst (
vl_wb3wb3_bridge wbwb3inst (
    // wishbone slave side
    // wishbone slave side
    .wbs_dat_i(wbs_dat_i),
    .wbs_dat_i(wbs_dat_i),
    .wbs_adr_i(wbs_adr_i),
    .wbs_adr_i(wbs_adr_i),
    .wbs_sel_i(wbs_sel_i),
    .wbs_sel_i(wbs_sel_i),

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