Line 250... |
Line 250... |
q <= reset_value;
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q <= reset_value;
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else
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else
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if (ce)
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if (ce)
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q <= d;
|
q <= d;
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endmodule
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endmodule
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|
module dff_ce_clear ( d, ce, clear, q, clk, rst);
|
|
parameter width = 1;
|
|
parameter reset_value = 0;
|
|
input [width-1:0] d;
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|
input ce, clk, rst;
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|
output reg [width-1:0] q;
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|
always @ (posedge clk or posedge rst)
|
|
if (rst)
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q <= reset_value;
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else
|
|
if (ce)
|
|
if (clear)
|
|
q <= {width{1'b0}};
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|
else
|
|
q <= d;
|
|
endmodule
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module dff_sr ( aclr, aset, clock, data, q);
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module dff_sr ( aclr, aset, clock, data, q);
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input aclr;
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input aclr;
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input aset;
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input aset;
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input clock;
|
input clock;
|
input data;
|
input data;
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Line 1563... |
Line 1579... |
dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
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dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
|
vl_fifo_cmp_async
|
vl_fifo_cmp_async
|
# (.addr_width(addr_width))
|
# (.addr_width(addr_width))
|
cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
|
cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
|
endmodule
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endmodule
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module vl_fifo_2r2w (
|
module vl_fifo_2r2w_async (
|
// a side
|
// a side
|
a_d, a_wr, a_fifo_full,
|
a_d, a_wr, a_fifo_full,
|
a_q, a_rd, a_fifo_empty,
|
a_q, a_rd, a_fifo_empty,
|
a_clk, a_rst,
|
a_clk, a_rst,
|
// b side
|
// b side
|
Line 1604... |
Line 1620... |
vl_fifo_1r1w_async_b (
|
vl_fifo_1r1w_async_b (
|
.d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
|
.d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
|
.q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
|
.q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
|
);
|
);
|
endmodule
|
endmodule
|
module vl_fifo_2r2w_simplex (
|
module vl_fifo_2r2w_async_simplex (
|
// a side
|
// a side
|
a_d, a_wr, a_fifo_full,
|
a_d, a_wr, a_fifo_full,
|
a_q, a_rd, a_fifo_empty,
|
a_q, a_rd, a_fifo_empty,
|
a_clk, a_rst,
|
a_clk, a_rst,
|
// b side
|
// b side
|