URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_actel.v] - Diff between revs 92 and 93

Rev 92	Rev 93
Line 1283...	Line 1283...
`end`	`end`
`endgenerate`	`endgenerate`
`always @ (posedge clk)`	`always @ (posedge clk)`
`q <= ram[adr];`	`q <= ram[adr];`
`endif	`endif
	`ifdef verilator
`// Function to access RAM (for use by Verilator).`	`// Function to access RAM (for use by Verilator).`
`function [31:0] get_mem;`	`function [31:0] get_mem;`
`// verilator public`	`// verilator public`
`input [addr_width-1:0] addr;`	`input [addr_width-1:0] addr;`
`get_mem = ram[addr];`	`get_mem = ram[addr];`
Line 1296...	Line 1297...
`// verilator public`	`// verilator public`
`input [addr_width-1:0] addr;`	`input [addr_width-1:0] addr;`
`input [data_width-1:0] data;`	`input [data_width-1:0] data;`
`ram[addr] = data;`	`ram[addr] = data;`
`endfunction // set_mem`	`endfunction // set_mem`
	`endif
`endmodule`	`endmodule`
`// ACTEL FPGA should not use logic to handle rw collision`	`// ACTEL FPGA should not use logic to handle rw collision`
`module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );`	`module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );`
`parameter data_width = 32;`	`parameter data_width = 32;`
`parameter addr_width = 8;`	`parameter addr_width = 8;`