URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Diff between revs 116 and 117

Rev 116	Rev 117
Line 2726...	Line 2726...
`vl_wb_ram # (`	`vl_wb_ram # (`
`.dat_width(dat_width),`	`.dat_width(dat_width),`
`.adr_width(shadow_mem_adr_width),`	`.adr_width(shadow_mem_adr_width),`
`.mem_size(shadow_mem_size),`	`.mem_size(shadow_mem_size),`
`.memory_init(shadow_mem_init),`	`.memory_init(shadow_mem_init),`
	`.memory_file(shadow_mem_file),`
`.mode(mode))`	`.mode(mode))`
`shadow_mem0 (`	`shadow_mem0 (`
`.wbs_dat_i(wbs_dat_i),`	`.wbs_dat_i(wbs_dat_i),`
`.wbs_adr_i(wbs_adr_i[shadow_mem_adr_width-1:0]),`	`.wbs_adr_i(wbs_adr_i[shadow_mem_adr_width-1:0]),`
`.wbs_sel_i(wbs_sel_i),`	`.wbs_sel_i(wbs_sel_i),`