OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Diff between revs 117 and 118

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 117 Rev 118
Line 1522... Line 1522...
   parameter mem_size = 1<<addr_width;
   parameter mem_size = 1<<addr_width;
   input [(data_width-1):0]      d_a;
   input [(data_width-1):0]      d_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_a;
   input [(addr_width-1):0]       adr_b;
   input [(addr_width-1):0]       adr_b;
   input                         we_a;
   input                         we_a;
   output [(data_width-1):0]      q_b;
   output reg [(data_width-1):0]          q_b;
   input                         clk_a, clk_b;
   input                         clk_a, clk_b;
   reg [(addr_width-1):0]         adr_b_reg;
 
   reg [data_width-1:0] ram [mem_size-1:0] ;
   reg [data_width-1:0] ram [mem_size-1:0] ;
    parameter memory_init = 0;
    parameter memory_init = 0;
    parameter memory_file = "vl_ram.vmem";
    parameter memory_file = "vl_ram.vmem";
    parameter debug = 0;
    parameter debug = 0;
    generate
    generate
Line 1551... Line 1550...
    endgenerate
    endgenerate
   always @ (posedge clk_a)
   always @ (posedge clk_a)
   if (we_a)
   if (we_a)
     ram[adr_a] <= d_a;
     ram[adr_a] <= d_a;
   always @ (posedge clk_b)
   always @ (posedge clk_b)
   adr_b_reg <= adr_b;
      q_b = ram[adr_b];
   assign q_b = ram[adr_b_reg];
 
endmodule
endmodule
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
   parameter data_width = 32;
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter addr_width = 8;
   parameter mem_size = 1<<addr_width;
   parameter mem_size = 1<<addr_width;
Line 1566... Line 1564...
   input                         we_a;
   input                         we_a;
   output [(data_width-1):0]      q_b;
   output [(data_width-1):0]      q_b;
   output reg [(data_width-1):0] q_a;
   output reg [(data_width-1):0] q_a;
   input                         clk_a, clk_b;
   input                         clk_a, clk_b;
   reg [(data_width-1):0]         q_b;
   reg [(data_width-1):0]         q_b;
   reg [data_width-1:0] ram [mem_szie-1:0] ;
   reg [data_width-1:0] ram [mem_size-1:0] ;
    parameter memory_init = 0;
    parameter memory_init = 0;
    parameter memory_file = "vl_ram.vmem";
    parameter memory_file = "vl_ram.vmem";
    parameter debug = 0;
    parameter debug = 0;
    generate
    generate
    if (memory_init == 1) begin : init_mem
    if (memory_init == 1) begin : init_mem

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.