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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Diff between revs 123 and 124

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Line 1701... Line 1701...
endmodule
endmodule
module vl_dpram_be_2r2w ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
module vl_dpram_be_2r2w ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
   parameter a_data_width = 32;
   parameter a_data_width = 32;
   parameter a_addr_width = 8;
   parameter a_addr_width = 8;
   parameter b_data_width = 64; //a_data_width;
   parameter b_data_width = 64; //a_data_width;
   localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
   //localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
 
   localparam b_addr_width =
 
        (a_data_width==b_data_width) ? aw_m :
 
        (a_data_width==b_data_width*2) ? aw_m+1 :
 
        (a_data_width==b_data_width*4) ? aw_m+2 :
 
        (a_data_width==b_data_width*8) ? aw_m+3 :
 
        (a_data_width==b_data_width*16) ? aw_m+4 :
 
        (a_data_width==b_data_width*32) ? aw_m+5 :
 
        (a_data_width==b_data_width/2) ? aw_m-1 :
 
        (a_data_width==b_data_width/4) ? aw_m-2 :
 
        (a_data_width==b_data_width/8) ? aw_m-3 :
 
        (a_data_width==b_data_width/16) ? aw_m-4 :
 
        (a_data_width==b_data_width/32) ? aw_m-5 : 0;
   localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
   localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
   parameter memory_init = 0;
   parameter memory_init = 0;
   parameter memory_file = "vl_ram.vmem";
   parameter memory_file = "vl_ram.vmem";
   parameter debug = 0;
   parameter debug = 0;
Line 2945... Line 2957...
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
);
);
parameter dw_s = 32;
parameter dw_s = 32;
parameter aw_s = 24;
parameter aw_s = 24;
parameter dw_m = dw_s;
parameter dw_m = dw_s;
localparam aw_m = dw_s * aw_s / dw_m;
//localparam aw_m = dw_s * aw_s / dw_m;
 
localparam aw_m =
 
        (dw_s==dw_m) ? aw_m :
 
        (dw_s==dw_m*2) ? aw_m+1 :
 
        (dw_s==dw_m*4) ? aw_m+2 :
 
        (dw_s==dw_m*8) ? aw_m+3 :
 
        (dw_s==dw_m*16) ? aw_m+4 :
 
        (dw_s==dw_m*32) ? aw_m+5 :
 
        (dw_s==dw_m/2) ? aw_m-1 :
 
        (dw_s==adw_m/4) ? aw_m-2 :
 
        (dw_s==dw_m/8) ? aw_m-3 :
 
        (dw_s==dw_m/16) ? aw_m-4 :
 
        (dw_s==dw_m/32) ? aw_m-5 : 0;
parameter wbs_max_burst_width = 4;
parameter wbs_max_burst_width = 4;
parameter wbs_mode = "B3";
parameter wbs_mode = "B3";
parameter async = 1; // wbs_clk != wbm_clk
parameter async = 1; // wbs_clk != wbm_clk
parameter nr_of_ways = 1;
parameter nr_of_ways = 1;
parameter aw_offset = 4; // 4 => 16 words per cache line
parameter aw_offset = 4; // 4 => 16 words per cache line

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