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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Diff between revs 142 and 143

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Rev 142 Rev 143
Line 3493... Line 3493...
module vl_reg_file (
module vl_reg_file (
    a1, a2, a3, wd3, we3, rd1, rd2, clk
    a1, a2, a3, wd3, we3, rd1, rd2, clk
);
);
parameter data_width = 32;
parameter data_width = 32;
parameter addr_width = 5;
parameter addr_width = 5;
 
parameter debug = 0;
input [addr_width-1:0] a1, a2, a3;
input [addr_width-1:0] a1, a2, a3;
input [data_width-1:0] wd3;
input [data_width-1:0] wd3;
input we3;
input we3;
output [data_width-1:0] rd1, rd2;
output [data_width-1:0] rd1, rd2;
input clk;
input clk;
 
generate
 
if (debug==1) begin : debug_we
 
    always @ (posedge clk)
 
        if (we)
 
            $display ("Value %h written at register %h : time %t", d, adr, $time);
 
end
 
endgenerate
vl_dpram_1r1w
vl_dpram_1r1w
    # ( .data_width(data_width), .addr_width(addr_width))
    # ( .data_width(data_width), .addr_width(addr_width))
    ram1 (
    ram1 (
        .d_a(wd3),
        .d_a(wd3),
        .adr_a(a3),
        .adr_a(a3),

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