OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Diff between revs 143 and 144

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 143 Rev 144
Line 3502... Line 3502...
output [data_width-1:0] rd1, rd2;
output [data_width-1:0] rd1, rd2;
input clk;
input clk;
generate
generate
if (debug==1) begin : debug_we
if (debug==1) begin : debug_we
    always @ (posedge clk)
    always @ (posedge clk)
        if (we)
        if (we3)
            $display ("Value %h written at register %h : time %t", d, adr, $time);
            $display ("Value %h written at register %h : time %t", d, adr, $time);
end
end
endgenerate
endgenerate
vl_dpram_1r1w
vl_dpram_1r1w
    # ( .data_width(data_width), .addr_width(addr_width))
    # ( .data_width(data_width), .addr_width(addr_width))

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.