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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Diff between revs 146 and 147

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Rev 146 Rev 147
Line 3497... Line 3497...
parameter debug = 0;
parameter debug = 0;
input [aw-1:0] a1, a2, a3;
input [aw-1:0] a1, a2, a3;
input [dw-1:0] wd3;
input [dw-1:0] wd3;
input we3;
input we3;
output [dw-1:0] rd1, rd2;
output [dw-1:0] rd1, rd2;
input clk;
input clk, rst;
wire [dw-1:0] rd1mem, rd2mem;
wire [dw-1:0] rd1mem, rd2mem;
reg [dw-1:0] wreg;
reg [dw-1:0] wreg;
reg sel1, sel2;
reg sel1, sel2;
generate
generate
if (debug==1) begin : debug_we
if (debug==1) begin : debug_we

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