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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Diff between revs 151 and 152

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Rev 151 Rev 152
Line 5279... Line 5279...
    opcode_sra: dout = (din >> s) | ({32{din[31]}} << (6'd32-{1'b0,s}));
    opcode_sra: dout = (din >> s) | ({32{din[31]}} << (6'd32-{1'b0,s}));
    //opcode_ror: dout = not yet implemented
    //opcode_ror: dout = not yet implemented
    default: dout = din << s;
    default: dout = din << s;
    endcase
    endcase
end
end
engenerate
endgenerate
endmodule
endmodule
// logic unit
// logic unit
// supporting the following logic functions
// supporting the following logic functions
//    a and b
//    a and b
//    a or  b
//    a or  b

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