Line 1936... |
Line 1936... |
input rd;
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input rd;
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output fifo_empty;
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output fifo_empty;
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input rd_clk;
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input rd_clk;
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input rd_rst;
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input rd_rst;
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wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
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wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
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/*
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vl_fifo_1r1w_async (
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d, wr, fifo_full, wr_clk, wr_rst,
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q, rd, fifo_empty, rd_clk, rd_rst
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);
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*/
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vl_cnt_gray_ce_bin
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vl_cnt_gray_ce_bin
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# ( .length(addr_width))
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# ( .length(addr_width))
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fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
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fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
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vl_cnt_gray_ce_bin
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vl_cnt_gray_ce_bin
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# (.length(addr_width))
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# (.length(addr_width))
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fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
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fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
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vl_dpram_1r1w
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vl_dpram_1r1w
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# (.data_width(data_width), .addr_width(addr_width))
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# (.data_width(data_width), .addr_width(addr_width))
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dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
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dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
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vl_fifo_cmp_async
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vl_fifo_cmp_async
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# (.addr_width(addr_width))
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# (.addr_width(addr_width))
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