Line 2419... |
Line 2419... |
# (.length(addr_width))
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# (.length(addr_width))
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fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
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fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
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vl_dpram_1r1w
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vl_dpram_1r1w
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# (.data_width(data_width), .addr_width(addr_width))
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# (.data_width(data_width), .addr_width(addr_width))
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dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
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dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
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vl_cnt_bin_ce_rew_zq_l1
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vl_cnt_bin_ce_rew_q_zq_l1
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# (.length(addr_width+1), .level1_value(1<<addr_width))
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# (.length(addr_width+1), .level1_value(1<<addr_width))
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fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
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fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
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endmodule
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endmodule
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// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
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// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
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// RAM is supposed to be larger than the two FIFOs
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// RAM is supposed to be larger than the two FIFOs
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