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//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

// Global buffer

// Global buffer

// usage:

// usage:

// use to enable global buffers for high fan out signals such as clock and reset

// use to enable global buffers for high fan out signals such as clock and reset

//altera

//altera

 // ALTERA

 // ALTERA

 //ACTEL

 //ACTEL

// sync reset

// sync reset

// input active lo async reset, normally from external reset generator and/or switch

// input active lo async reset, normally from external reset generator and/or switch

// output active high global reset sync with two DFFs 

// output active high global reset sync with two DFFs 

reg [1:0] tmp;

reg [1:0] tmp;

always @ (posedge clk or negedge rst_n_i)

always @ (posedge clk or negedge rst_n_i)

if (!rst_n_i)

if (!rst_n_i)

        tmp <= 2'b11;

        tmp <= 2'b11;

else

else

vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));

vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));

endmodule

endmodule

// vl_pll

// vl_pll

///////////////////////////////////////////////////////////////////////////////

///////////////////////////////////////////////////////////////////////////////

`timescale 1 ps/1 ps

`timescale 1 ps/1 ps

parameter lock_delay = 2000000;

parameter lock_delay = 2000000;

input clk_i, rst_n_i;

input clk_i, rst_n_i;

output lock;

output lock;

output reg [0:number_of_clk-1] clk_o;

output reg [0:number_of_clk-1] clk_o;

output [0:number_of_clk-1] rst_o;

output [0:number_of_clk-1] rst_o;

always

always

     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];

     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];

generate if (number_of_clk > 1)

generate if (number_of_clk > 1)

always

always

     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];

     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];

endgenerate

endgenerate

generate if (number_of_clk > 2)

generate if (number_of_clk > 2)

always

always

     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];

     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];

endgenerate

endgenerate

always

always

     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];

     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];

endgenerate

endgenerate

always

always

     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];

     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];

endgenerate

endgenerate

genvar i;

genvar i;

generate for (i=0;i<number_of_clk;i=i+1) begin: clock

generate for (i=0;i<number_of_clk;i=i+1) begin: clock

     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));

     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));

end

end

endgenerate

endgenerate

endmodule

endmodule

genvar i;

genvar i;

generate for (i=0;i<number_of_clk;i=i+1) begin: clock

generate for (i=0;i<number_of_clk;i=i+1) begin: clock

end

end

endgenerate

endgenerate

endmodule

endmodule

///////////////////////////////////////////////////////////////////////////////

///////////////////////////////////////////////////////////////////////////////

 //altera

 //altera

 //actel

 //actel

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

////                                                              ////

////                                                              ////

parameter wbs_adr  = 1'b0;

parameter wbs_adr  = 1'b0;

parameter wbs_data = 1'b1;

parameter wbs_data = 1'b1;

parameter wbm_adr0 = 2'b00;

parameter wbm_adr0 = 2'b00;

parameter wbm_adr1 = 2'b01;

parameter wbm_adr1 = 2'b01;

parameter wbm_data = 2'b10;

parameter wbm_data = 2'b10;

reg [1:0] wbs_bte_reg;

reg [1:0] wbs_bte_reg;

reg wbs;

reg wbs;

wire wbs_eoc_alert, wbm_eoc_alert;

wire wbs_eoc_alert, wbm_eoc_alert;

reg wbs_eoc, wbm_eoc;

reg wbs_eoc, wbm_eoc;

reg [1:0] wbm;

reg [1:0] wbm;

                wbm_eoc <= 1'b1;

                wbm_eoc <= 1'b1;

always @ (posedge wbm_clk or posedge wbm_rst)

always @ (posedge wbm_clk or posedge wbm_rst)

if (wbm_rst)

if (wbm_rst)

        wbm <= wbm_adr0;

        wbm <= wbm_adr0;

else

else

assign b_d = {wbm_dat_i,4'b1111};

assign b_d = {wbm_dat_i,4'b1111};

assign b_wr = !wbm_we_o & wbm_ack_i;

assign b_wr = !wbm_we_o & wbm_ack_i;

assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);

assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);

assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]

assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]

                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :

                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :

                   1'b0;

                   1'b0;

assign b_rd = b_rd_adr | b_rd_data;

assign b_rd = b_rd_adr | b_rd_data;

vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));

vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));

vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));

vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));

assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;

assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;

        .cke(wbm_ack_i),

        .cke(wbm_ack_i),

        .clear(wbm_eoc),

        .clear(wbm_eoc),

        .q(wbm_count),

        .q(wbm_count),

        .rst(wbm_rst),

        .rst(wbm_rst),

        .clk(wbm_clk));

        .clk(wbm_clk));

always @ (posedge wbm_clk or posedge wbm_rst)

always @ (posedge wbm_clk or posedge wbm_rst)

if (wbm_rst)

if (wbm_rst)

        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};

        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};

else begin

else begin

        if (wbm==wbm_adr0 & !b_fifo_empty)

        if (wbm==wbm_adr0 & !b_fifo_empty)

    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);

    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);

    parameter adr_hi = 31;

    parameter adr_hi = 31;

    parameter adr_lo = 28;

    parameter adr_lo = 28;

    parameter adr_sel = 4'hf;

    parameter adr_sel = 4'hf;

    parameter addr_width = 5;

    parameter addr_width = 5;

    input [adr_hi:2]    wb_adr_i;

    input [adr_hi:2]    wb_adr_i;

    input               wb_stb_i;

    input               wb_stb_i;

    input               wb_cyc_i;

    input               wb_cyc_i;

    output [31:0]        wb_dat_o;

    output [31:0]        wb_dat_o;

    output              wb_ack_o;

    output              wb_ack_o;

always @ (posedge wb_clk or posedge wb_rst)

always @ (posedge wb_clk or posedge wb_rst)

    if (wb_rst)

    if (wb_rst)

        wb_dat <= 32'h15000000;

        wb_dat <= 32'h15000000;

    else

    else

         case (wb_adr_i[addr_width-1:2])

         case (wb_adr_i[addr_width-1:2])

           /*

           /*

            // Zero r0 and jump to 0x00000100

            // Zero r0 and jump to 0x00000100

            0 : wb_dat <= 32'h18000000;

            0 : wb_dat <= 32'h18000000;

            1 : wb_dat <= 32'hA8200000;

            1 : wb_dat <= 32'hA8200000;

            2 : wb_dat <= 32'hA8C00100;

            2 : wb_dat <= 32'hA8C00100;

output [31:0] wbsb_dat_o;

output [31:0] wbsb_dat_o;

output wbsb_ack_o;

output wbsb_ack_o;

input wbsb_clk, wbsb_rst;

input wbsb_clk, wbsb_rst;

wire wbsa_dat_tmp, wbsb_dat_tmp;

wire wbsa_dat_tmp, wbsb_dat_tmp;

vl_dpram_2r2w # (

vl_dpram_2r2w # (

dpram0(

dpram0(

    .d_a(wbsa_dat_i),

    .d_a(wbsa_dat_i),

    .q_a(wbsa_dat_tmp),

    .q_a(wbsa_dat_tmp),

    .adr_a(wbsa_adr_i),

    .adr_a(wbsa_adr_i),

    .we_a(wbsa_we_i),

    .we_a(wbsa_we_i),

    .d_b(wbsb_dat_i),

    .d_b(wbsb_dat_i),

    .q_b(wbsb_dat_tmp),

    .q_b(wbsb_dat_tmp),

    .adr_b(wbsb_adr_i),

    .adr_b(wbsb_adr_i),

    .we_b(wbsb_we_i),

    .we_b(wbsb_we_i),

    .clk_b(wbsb_clk) );

    .clk_b(wbsb_clk) );

    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};

    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};

endgenerate

endgenerate

    assign wbsa_dat_o = wbsa_dat_tmp;

    assign wbsa_dat_o = wbsa_dat_tmp;

endgenerate

endgenerate

    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};

    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};

endgenerate

endgenerate

    assign wbsb_dat_o = wbsb_dat_tmp;

    assign wbsb_dat_o = wbsb_dat_tmp;

endgenerate

endgenerate

vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));

vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));

vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));

vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));

endmodule

endmodule