| Line 2047... |
Line 2047... |
assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
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assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
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assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
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assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
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assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
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assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
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endmodule
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endmodule
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// WB RAM with byte enable
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// WB RAM with byte enable
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module vl_wb_b3_ram_be (
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wb_dat_i, wb_adr_i, wb_cti_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
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wb_dat_o, wb_ack_o, wb_clk, wb_rst);
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parameter dat_width = 32;
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parameter adr_width = 8;
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input [dat_width-1:0] wb_dat_i;
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input [adr_width-1:0] wb_adr_i;
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input [2:0] wb_cti_i;
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input [dat_width/8-1:0] wb_sel_i;
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input wb_we_i, wb_stb_i, wb_cyc_i;
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output [dat_width-1:0] wb_dat_o;
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reg [dat_width-1:0] wb_dat_o;
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output wb_stall_o;
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output wb_ack_o;
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reg wb_ack_o;
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input wb_clk, wb_rst;
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wire [dat_width/8-1:0] cke;
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generate
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if (dat_width==32) begin
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reg [7:0] ram3 [1<<(adr_width-2)-1:0];
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reg [7:0] ram2 [1<<(adr_width-2)-1:0];
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reg [7:0] ram1 [1<<(adr_width-2)-1:0];
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reg [7:0] ram0 [1<<(adr_width-2)-1:0];
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assign cke = wb_sel_i & {(dat_width/8){wb_we_i}};
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always @ (posedge wb_clk)
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begin
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if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
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if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
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if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
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if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
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end
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always @ (posedge wb_clk or posedge wb_rst)
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begin
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if (wb_rst)
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wb_dat_o <= 32'h0;
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else
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wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
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end
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end
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endgenerate
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always @ (posedge wb_clk or posedge wb_rst)
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if (wb_rst)
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wb_ack_o <= 1'b0;
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else
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if (wb_cti_i=3'b000 | wb_cti_i=3'b111)
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wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o;
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else
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wb_ack_o <= wb_stb_i & wb_cyc_i;
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endmodule
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// WB RAM with byte enable
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module vl_wb_b4_ram_be (
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module vl_wb_b4_ram_be (
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wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
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wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
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wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
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wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
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parameter dat_width = 32;
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parameter dat_width = 32;
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parameter adr_width = 8;
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parameter adr_width = 8;
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| Line 2076... |
Line 2126... |
begin
|
begin
|
if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
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if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
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if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
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if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
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if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
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if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
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if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
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if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
|
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end
|
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always @ (posedge wb_clk or posedge wb_rst)
|
|
begin
|
|
if (wb_rst)
|
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wb_dat_o <= 32'h0;
|
|
else
|
wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
|
wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
always @ (posedge wb_clk or posedge wb_rst)
|
always @ (posedge wb_clk or posedge wb_rst)
|
