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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Diff between revs 56 and 59

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Rev 56 Rev 59
Line 2047... Line 2047...
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
endmodule
endmodule
// WB RAM with byte enable
// WB RAM with byte enable
 
module vl_wb_b3_ram_be (
 
    wb_dat_i, wb_adr_i, wb_cti_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
 
    wb_dat_o, wb_ack_o, wb_clk, wb_rst);
 
    parameter dat_width = 32;
 
    parameter adr_width = 8;
 
input [dat_width-1:0] wb_dat_i;
 
input [adr_width-1:0] wb_adr_i;
 
input [2:0] wb_cti_i;
 
input [dat_width/8-1:0] wb_sel_i;
 
input wb_we_i, wb_stb_i, wb_cyc_i;
 
output [dat_width-1:0] wb_dat_o;
 
reg [dat_width-1:0] wb_dat_o;
 
output wb_stall_o;
 
output wb_ack_o;
 
reg wb_ack_o;
 
input wb_clk, wb_rst;
 
wire [dat_width/8-1:0] cke;
 
generate
 
if (dat_width==32) begin
 
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
 
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
 
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
 
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
 
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}};
 
    always @ (posedge wb_clk)
 
    begin
 
        if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
 
        if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
 
        if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
 
        if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
 
    end
 
    always @ (posedge wb_clk or posedge wb_rst)
 
    begin
 
        if (wb_rst)
 
            wb_dat_o <= 32'h0;
 
        else
 
            wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
 
    end
 
end
 
endgenerate
 
always @ (posedge wb_clk or posedge wb_rst)
 
if (wb_rst)
 
    wb_ack_o <= 1'b0;
 
else
 
    if (wb_cti_i=3'b000 | wb_cti_i=3'b111)
 
        wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o;
 
    else
 
        wb_ack_o <= wb_stb_i & wb_cyc_i;
 
endmodule
 
// WB RAM with byte enable
module vl_wb_b4_ram_be (
module vl_wb_b4_ram_be (
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
    wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
    wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
    parameter dat_width = 32;
    parameter dat_width = 32;
    parameter adr_width = 8;
    parameter adr_width = 8;
Line 2076... Line 2126...
    begin
    begin
        if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
        if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
        if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
        if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
        if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
        if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
        if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
        if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
 
    end
 
    always @ (posedge wb_clk or posedge wb_rst)
 
    begin
 
        if (wb_rst)
 
            wb_dat_o <= 32'h0;
 
        else
        wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
        wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
    end
    end
end
end
endgenerate
endgenerate
always @ (posedge wb_clk or posedge wb_rst)
always @ (posedge wb_clk or posedge wb_rst)

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