Subversion Repositories versatile_library

    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];

    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];

    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];

    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];

end

end

endgenerate

endgenerate

generate

generate

    vl_spr sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));

    vl_spr sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));

end

end

endgenerate

endgenerate

    assign sel = select | state;

    assign sel = select | state;

    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));

    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));

input [cw-1:0] wb_cti_i;

input [cw-1:0] wb_cti_i;

input [bw-1:0] wb_bte_i;

input [bw-1:0] wb_bte_i;

input [sw-1:0] wb_sel_i;

input [sw-1:0] wb_sel_i;

input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i;

input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i;

output [dw-1:0] wb_dat_o;

output [dw-1:0] wb_dat_o;

output wb_ack_o;

output wb_ack_o;

input wb_clk, wb_rst;

input wb_clk, wb_rst;

wire [sw-1:0] cke;

wire [sw-1:0] cke;

// local wb slave

// local wb slave

wire [dat_size-1:0] wbs_dat_i;

wire [dat_size-1:0] wbs_dat_i;

wire [adr_size-1:0] wbs_adr_i;

wire [adr_size-1:0] wbs_adr_i;