URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Diff between revs 69 and 70

Rev 69	Rev 70
Line 2166...	Line 2166...
`localparam aw = (adr_size - adr_lo);`	`localparam aw = (adr_size - adr_lo);`
`localparam dw = dat_size;`	`localparam dw = dat_size;`
`localparam sw = dat_size/8;`	`localparam sw = dat_size/8;`
`localparam cw = 3;`	`localparam cw = 3;`
`localparam bw = 2;`	`localparam bw = 2;`
`input [dw-1:0] wb_dat_i;`	`input [dw-1:0] wbs_dat_i;`
`input [aw-1:0] wb_adr_i;`	`input [aw-1:0] wbs_adr_i;`
`input [cw-1:0] wb_cti_i;`	`input [cw-1:0] wbs_cti_i;`
`input [bw-1:0] wb_bte_i;`	`input [bw-1:0] wbs_bte_i;`
`input [sw-1:0] wb_sel_i;`	`input [sw-1:0] wbs_sel_i;`
`input wb_we_i, wb_stb_i, wb_cyc_i;`	`input wbs_we_i, wbs_stb_i, wbs_cyc_i;`
`output [dw-1:0] wb_dat_o;`	`output [dw-1:0] wbs_dat_o;`
`output wb_ack_o;`	`output wbs_ack_o;`
`input wb_clk, wb_rst;`	`input wbs_clk, wbs_rst;`
`wire [sw-1:0] cke;`	`wire [sw-1:0] cke;`
`reg wbs_ack_o;`	`reg wbs_ack_o;`
`vl_ram_be # (`	`vl_ram_be # (`
`.data_width(dat_size),`	`.data_width(dat_size),`
`.addr_width(adr_size),`	`.addr_width(adr_size),`