| Line 1507... |
Line 1507... |
input we_b;
|
input we_b;
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input clk_a, clk_b;
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input clk_a, clk_b;
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reg [(b_data_width-1):0] q_b;
|
reg [(b_data_width-1):0] q_b;
|
generate
|
generate
|
if (a_data_width==32 & b_data_width==64) begin : inst32to64
|
if (a_data_width==32 & b_data_width==64) begin : inst32to64
|
wire [63:0] temp;
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wire [63:0] tmp;
|
vl_dpram_2r2w
|
vl_dpram_2r2w
|
# (.data_width(8), .addr_width(b_addr_width-3))
|
# (.data_width(8), .addr_width(b_addr_width-3))
|
ram0 (
|
ram0 (
|
.d_a(d_a[7:0]),
|
.d_a(d_a[7:0]),
|
.q_a(tmp[7:0]),
|
.q_a(tmp[7:0]),
|
| Line 2094... |
Line 2094... |
always @ (posedge wbs_clk or posedge wbs_rst)
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
if (wbs_rst)
|
if (wbs_rst)
|
wbs_eoc <= 1'b0;
|
wbs_eoc <= 1'b0;
|
else
|
else
|
if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
|
if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
|
wbs_eoc <= wbs_bte_i==linear;
|
wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_==3'b111);
|
else if (wbs_eoc_alert & (a_rd | a_wr))
|
else if (wbs_eoc_alert & (a_rd | a_wr))
|
wbs_eoc <= 1'b1;
|
wbs_eoc <= 1'b1;
|
vl_cnt_shreg_ce_clear # ( .length(16))
|
vl_cnt_shreg_ce_clear # ( .length(16))
|
cnt0 (
|
cnt0 (
|
.cke(wbs_ack_o),
|
.cke(wbs_ack_o),
|
| Line 2223... |
Line 2223... |
);
|
);
|
endmodule
|
endmodule
|
module vl_wb3avalon_bridge (
|
module vl_wb3avalon_bridge (
|
// wishbone slave side
|
// wishbone slave side
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
|
// wishbone master side
|
// avalon master side
|
readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
|
readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
|
input [31:0] wbs_dat_i;
|
input [31:0] wbs_dat_i;
|
input [31:2] wbs_adr_i;
|
input [31:2] wbs_adr_i;
|
input [3:0] wbs_sel_i;
|
input [3:0] wbs_sel_i;
|
input [1:0] wbs_bte_i;
|
input [1:0] wbs_bte_i;
|
| Line 2262... |
Line 2262... |
(wbm_bte_o==2'b10) ? 4'd8 :
|
(wbm_bte_o==2'b10) ? 4'd8 :
|
4'd16;
|
4'd16;
|
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o;
|
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o;
|
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o;
|
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o;
|
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest);
|
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest);
|
vl_wb3wb3_bridge (
|
vl_wb3wb3_bridge wbwb3inst (
|
// wishbone slave side
|
// wishbone slave side
|
.wbs_dat_i(wbs_dat_i),
|
.wbs_dat_i(wbs_dat_i),
|
.wbs_adr_i(wbs_adr_i),
|
.wbs_adr_i(wbs_adr_i),
|
.wbs_sel_i(wbs_sel_i),
|
.wbs_sel_i(wbs_sel_i),
|
.wbs_bte_i(wbs_bte_i),
|
.wbs_bte_i(wbs_bte_i),
|
