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https://opencores.org/ocsvn/versatile_library/versatile_library/trunk
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| Rev 78 |
Rev 79 |
| Line 2250... |
Line 2250... |
input rst;
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input rst;
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wire [1:0] wbm_bte_o;
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wire [1:0] wbm_bte_o;
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wire [2:0] wbm_cti_o;
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wire [2:0] wbm_cti_o;
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wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
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wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
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reg last_cyc;
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reg last_cyc;
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reg [3:0] counter;
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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if (rst)
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if (rst)
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last_cyc <= 1'b0;
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last_cyc <= 1'b0;
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else
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else
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last_cyc <= wbm_cyc_o;
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last_cyc <= wbm_cyc_o;
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always @ (posedge clk or posedge rst)
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if (rst)
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read <= 1'b0;
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else
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if (!last_cyc & wbm_cyc_o)
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read <= 1'b1;
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else if (!waitrequest)
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read <= 1'b0;
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assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
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assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
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assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
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assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
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(wbm_bte_o==2'b10) ? 4'd8 :
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(wbm_bte_o==2'b10) ? 4'd8 :
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(wbm_bte_o==2'b11) ? 4'd16:
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(wbm_bte_o==2'b11) ? 4'd16:
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4'd1;
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4'd1;
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assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o;
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assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o;
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assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest);
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assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest);
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always @ (posedge clk or posedge rst)
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if (rst) begin
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counter <= 4'd0;
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write <= 1'b0;
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end else
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if (!waitrequest & last_cyc & wbm_cyc_o) begin
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write <= 1'b1;
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counter <= burstcount -1;
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end else if (waitrequest & last_cyc & wbm_cyc_o) begin
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write <= 1'b1;
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counter <= burstcount;
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end else if (!waitrequst) begin
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counter <= counter - 4'd1;
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write <= (counter!=4'd0 & wbm_stb_o)
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end
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vl_wb3wb3_bridge wbwb3inst (
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vl_wb3wb3_bridge wbwb3inst (
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// wishbone slave side
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// wishbone slave side
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.wbs_dat_i(wbs_dat_i),
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.wbs_dat_i(wbs_dat_i),
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.wbs_adr_i(wbs_adr_i),
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.wbs_adr_i(wbs_adr_i),
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.wbs_sel_i(wbs_sel_i),
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.wbs_sel_i(wbs_sel_i),
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