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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Diff between revs 80 and 81

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Rev 80 Rev 81
Line 2239... Line 2239...
input [31:0] readdata;
input [31:0] readdata;
output [31:0] writedata;
output [31:0] writedata;
output [31:2] address;
output [31:2] address;
output [3:0]  be;
output [3:0]  be;
output write;
output write;
output reg read;
output read;
output beginbursttransfer;
output beginbursttransfer;
output [3:0] burstcount;
output [3:0] burstcount;
input readdatavalid;
input readdatavalid;
input waitrequest;
input waitrequest;
input clk;
input clk;
Line 2256... Line 2256...
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
if (rst)
if (rst)
    last_cyc <= 1'b0;
    last_cyc <= 1'b0;
else
else
    last_cyc <= wbm_cyc_o;
    last_cyc <= wbm_cyc_o;
always @ (posedge clk or posedge rst)
/*
if (rst)
always @ (posedge clk or posedge rst)
    read <= 1'b0;
if (rst)
else
    read <= 1'b0;
    if (!last_cyc & wbm_cyc_o & !wbm_we_o)
else
        read <= 1'b1;
    if (!last_cyc & wbm_cyc_o & !wbm_we_o)
    else if (!waitrequest)
        read <= 1'b1;
        read <= 1'b0;
    else if (!waitrequest)
 
        read <= 1'b0;
 
*/
 
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & counter!=4'd0;
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
                    (wbm_bte_o==2'b10) ? 4'd8 :
                    (wbm_bte_o==2'b10) ? 4'd8 :
                    (wbm_bte_o==2'b11) ? 4'd16:
                    (wbm_bte_o==2'b11) ? 4'd16:
                    4'd1;
                    4'd1;
Line 2283... Line 2286...
            counter <= burstcount;
            counter <= burstcount;
        end else if (!waitrequest & wbm_stb_o) begin
        end else if (!waitrequest & wbm_stb_o) begin
            counter <= counter - 4'd1;
            counter <= counter - 4'd1;
        end
        end
    end
    end
assign write = wbm_cyc & wbm_stb_o & wbm_we_o & counter!=4'd0;
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
vl_wb3wb3_bridge wbwb3inst (
vl_wb3wb3_bridge wbwb3inst (
    // wishbone slave side
    // wishbone slave side
    .wbs_dat_i(wbs_dat_i),
    .wbs_dat_i(wbs_dat_i),
    .wbs_adr_i(wbs_adr_i),
    .wbs_adr_i(wbs_adr_i),
    .wbs_sel_i(wbs_sel_i),
    .wbs_sel_i(wbs_sel_i),

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