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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Diff between revs 81 and 82

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Rev 81 Rev 82
Line 2251... Line 2251...
wire [1:0] wbm_bte_o;
wire [1:0] wbm_bte_o;
wire [2:0] wbm_cti_o;
wire [2:0] wbm_cti_o;
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
reg last_cyc;
reg last_cyc;
reg [3:0] counter;
reg [3:0] counter;
 
reg read_busy;
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
if (rst)
if (rst)
    last_cyc <= 1'b0;
    last_cyc <= 1'b0;
else
else
    last_cyc <= wbm_cyc_o;
    last_cyc <= wbm_cyc_o;
/*
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
if (rst)
if (rst)
    read_busy <= 1'b0;
    read <= 1'b0;
else
else
    if (read & !waitrequest)
    if (!last_cyc & wbm_cyc_o & !wbm_we_o)
        read_busy <= 1'b1;
        read <= 1'b1;
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
    else if (!waitrequest)
        read_busy <= 1'b0;
        read <= 1'b0;
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
*/
 
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & counter!=4'd0;
 
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
                    (wbm_bte_o==2'b10) ? 4'd8 :
                    (wbm_bte_o==2'b10) ? 4'd8 :
                    (wbm_bte_o==2'b11) ? 4'd16:
                    (wbm_bte_o==2'b11) ? 4'd16:
                    4'd1;
                    4'd1;
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest);
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
always @ (posedge clk or posedge rst)
always @ (posedge clk or posedge rst)
if (rst) begin
if (rst) begin
    counter <= 4'd0;
    counter <= 4'd0;
end else
end else
    if (wbm_we_o) begin
    if (wbm_we_o) begin

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