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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Diff between revs 82 and 83

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Rev 82 Rev 83
Line 2035... Line 2035...
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// async wb3 - wb3 bridge
// async wb3 - wb3 bridge
`timescale 1ns/1ns
`timescale 1ns/1ns
 
module vl_wb_adr_inc ( cyc_i, stb_i, cti_i, bte_i, adr_i, ack_o, adr_o, clk, rst);
 
parameter adr_width = 10;
 
parameter max_burst_width = 4;
 
input cyc_i, stb_i;
 
input [2:0] cti_i;
 
input [1:0] bte_i;
 
input [adr_width-1:0] adr_i;
 
output [adr_width-1:0] adr_o;
 
output ack_o;
 
input clk, rst;
 
reg [adr_width-1:0] adr;
 
generate
 
if (max_burst_width==0) begin : inst_0
 
    reg ack_o;
 
    assign adr_o = adr_i;
 
    always @ (posedge clk or posedge rst)
 
    if (rst)
 
        ack_o <= 1'b0;
 
    else
 
        ack_o <= cyc_i & stb_i & !ack_o;
 
end else begin
 
    wire [max_burst_width-1:0] to_adr;
 
    reg [1:0] last_cycle;
 
    localparam idle = 2'b00;
 
    localparam cyc  = 2'b01;
 
    localparam ws   = 2'b10;
 
    localparam eoc  = 2'b11;
 
    always @ (posedge clk or posedge rst)
 
    if (rst)
 
        last_cycle <= idle;
 
    else
 
        last_cycle <= (!cyc_i) ? idle :
 
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? eoc :
 
                      (cyc_i & !stb_i) ? ws :
 
                      cyc;
 
    assign to_adr = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
 
    assign adr_o[max_burst_width-1:0] = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
 
    assign ack_o = last_cycle == cyc;
 
end
 
endgenerate
 
generate
 
if (max_burst_width==2) begin : inst_2
 
    always @ (posedge clk or posedge rst)
 
    if (rst)
 
        adr <= 2'h0;
 
    else
 
        if (cyc_i & stb_i)
 
            adr[1:0] <= to_adr[1:0] + 2'd1;
 
        else
 
            adr <= to_adr[1:0];
 
end
 
endgenerate
 
generate
 
if (max_burst_width==3) begin : inst_3
 
    always @ (posedge clk or posedge rst)
 
    if (rst)
 
        adr <= 3'h0;
 
    else
 
        if (cyc_i & stb_i)
 
            case (bte_i)
 
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
 
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
 
            endcase
 
        else
 
            adr <= to_adr[2:0];
 
end
 
endgenerate
 
generate
 
if (max_burst_width==4) begin : inst_4
 
    always @ (posedge clk or posedge rst)
 
    if (rst)
 
        adr <= 4'h0;
 
    else
 
        if (cyc_i & stb_i)
 
            case (bte_i)
 
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
 
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
 
            default: adr[3:0] <= to_adr + 4'd1;
 
            endcase
 
        else
 
            adr <= to_adr[3:0];
 
end
 
endgenerate
 
generate
 
if (adr_width > max_burst_width) begin : pass_through
 
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
 
end
 
endgenerate
 
endmodule
 
// async wb3 - wb3 bridge
 
`timescale 1ns/1ns
module vl_wb3wb3_bridge (
module vl_wb3wb3_bridge (
        // wishbone slave side
        // wishbone slave side
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
        // wishbone master side
        // wishbone master side
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
Line 2230... Line 2321...
input [31:0] wbs_dat_i;
input [31:0] wbs_dat_i;
input [31:2] wbs_adr_i;
input [31:2] wbs_adr_i;
input [3:0]  wbs_sel_i;
input [3:0]  wbs_sel_i;
input [1:0]  wbs_bte_i;
input [1:0]  wbs_bte_i;
input [2:0]  wbs_cti_i;
input [2:0]  wbs_cti_i;
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
input wbs_we_i;
 
input wbs_cyc_i;
 
input wbs_stb_i;
output [31:0] wbs_dat_o;
output [31:0] wbs_dat_o;
output wbs_ack_o;
output wbs_ack_o;
input wbs_clk, wbs_rst;
input wbs_clk, wbs_rst;
input [31:0] readdata;
input [31:0] readdata;
output [31:0] writedata;
output [31:0] writedata;
Line 2550... Line 2643...
    wbs_dat_o, wbs_ack_o, wb_clk, wb_rst);
    wbs_dat_o, wbs_ack_o, wb_clk, wb_rst);
parameter adr_size = 16;
parameter adr_size = 16;
parameter adr_lo   = 2;
parameter adr_lo   = 2;
parameter mem_size = 1<<16;
parameter mem_size = 1<<16;
parameter dat_size = 32;
parameter dat_size = 32;
 
parameter max_burst_width = 4;
parameter memory_init = 1;
parameter memory_init = 1;
parameter memory_file = "vl_ram.vmem";
parameter memory_file = "vl_ram.vmem";
localparam aw = (adr_size - adr_lo);
localparam aw = (adr_size - adr_lo);
localparam dw = dat_size;
localparam dw = dat_size;
localparam sw = dat_size/8;
localparam sw = dat_size/8;
Line 2566... Line 2660...
input [sw-1:0] wbs_sel_i;
input [sw-1:0] wbs_sel_i;
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
output [dw-1:0] wbs_dat_o;
output [dw-1:0] wbs_dat_o;
output wbs_ack_o;
output wbs_ack_o;
input wb_clk, wb_rst;
input wb_clk, wb_rst;
wire [sw-1:0] cke;
 
reg wbs_ack_o;
reg wbs_ack_o;
 
wire [aw-1:0] adr;
vl_ram_be # (
vl_ram_be # (
    .data_width(dat_size),
    .data_width(dat_size),
    .addr_width(adr_size-2),
    .addr_width(aw),
    .mem_size(mem_size),
    .mem_size(mem_size),
    .memory_init(memory_init),
    .memory_init(memory_init),
    .memory_file(memory_file))
    .memory_file(memory_file))
ram0(
ram0(
    .d(wbs_dat_i),
    .d(wbs_dat_i),
    .adr(wbs_adr_i[adr_size-1:2]),
    .adr(adr),
    .be(wbs_sel_i),
    .be(wbs_sel_i),
    .we(wbs_we_i),
    .we(wbs_we_i),
    .q(wbs_dat_o),
    .q(wbs_dat_o),
    .clk(wb_clk)
    .clk(wb_clk)
);
);
always @ (posedge wb_clk or posedge wb_rst)
vl_wb_adr_inc # ( .adr_width(aw), .max_burst_width(max_burst_width)) adr_inc0 (
if (wb_rst)
    .cyc_i(wbs_cyc_i),
    wbs_ack_o <= 1'b0;
    .stb_i(wbs_stb_i),
else
    .cti_i(wbs_cti_i),
    if (wbs_cti_i==3'b000 | wbs_cti_i==3'b111)
    .bte_i(wbs_bte_i),
        wbs_ack_o <= wbs_stb_i & wbs_cyc_i & !wbs_ack_o;
    .adr_i(wbs_adr_i),
    else
    .ack_o(wbs_ack_o),
        wbs_ack_o <= wbs_stb_i & wbs_cyc_i;
    .adr_o(adr),
 
    .clk(wb_clk),
 
    .rst(wb_rst));
endmodule
endmodule
// WB RAM with byte enable
// WB RAM with byte enable
module vl_wb_b4_ram_be (
module vl_wb_b4_ram_be (
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
    wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
    wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);

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