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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Diff between revs 83 and 85

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Rev 83 Rev 85
Line 1355... Line 1355...
   input                         clk;
   input                         clk;
`ifdef SYSTEMVERILOG
`ifdef SYSTEMVERILOG
   logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
   logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
`else
`else
   reg [data_width-1:0] ram [mem_size-1:0];
   reg [data_width-1:0] ram [mem_size-1:0];
 
    wire [data_width/8-1:0] cke;
`endif
`endif
   parameter memory_init = 0;
   parameter memory_init = 0;
   parameter memory_file = "vl_ram.vmem";
   parameter memory_file = "vl_ram.vmem";
   generate if (memory_init) begin : init_mem
   generate if (memory_init) begin : init_mem
   initial
   initial
Line 1371... Line 1372...
// use a multi-dimensional packed array
// use a multi-dimensional packed array
//to model individual bytes within the word
//to model individual bytes within the word
always_ff@(posedge clk)
always_ff@(posedge clk)
begin
begin
    if(we) begin // note: we should have a for statement to support any bus width
    if(we) begin // note: we should have a for statement to support any bus width
        if(be[3]) ram[adr[addr_width-2:0]][3] <= d[31:24];
        if(be[3]) ram[adr[3] <= d[31:24];
        if(be[2]) ram[adr[addr_width-2:0]][2] <= d[23:16];
        if(be[2]) ram[adr[2] <= d[23:16];
        if(be[1]) ram[adr[addr_width-2:0]][1] <= d[15:8];
        if(be[1]) ram[adr[1] <= d[15:8];
        if(be[0]) ram[adr[addr_width-2:0]][0] <= d[7:0];
        if(be[0]) ram[adr[0] <= d[7:0];
    end
    end
    q <= ram[adr];
    q <= ram[adr];
end
end
`else
`else
 
assign cke = {data_width/8{we}} & be;
   genvar i;
   genvar i;
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
      always @ (posedge clk)
      always @ (posedge clk)
      if (we & be[i])
      if (cke[i])
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
   end
   end
   endgenerate
   endgenerate
   always @ (posedge clk)
   always @ (posedge clk)
      q <= ram[adr];
      q <= ram[adr];
`endif
`endif
 
   // Function to access RAM (for use by Verilator).
 
   function [31:0] get_mem;
 
      // verilator public
 
      input [aw-1:0]             addr;
 
      get_mem = ram[addr];
 
   endfunction // get_mem
 
   // Function to write RAM (for use by Verilator).
 
   function set_mem;
 
      // verilator public
 
      input [aw-1:0]             addr;
 
      input [dw-1:0]             data;
 
      ram[addr] = data;
 
   endfunction // set_mem
endmodule
endmodule
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
   parameter data_width = 32;
   parameter data_width = 32;
   parameter addr_width = 8;
   parameter addr_width = 8;
   parameter mem_size = 1<<addr_width;
   parameter mem_size = 1<<addr_width;
Line 2035... Line 2050...
//// from http://www.opencores.org/lgpl.shtml                     ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// async wb3 - wb3 bridge
// async wb3 - wb3 bridge
`timescale 1ns/1ns
`timescale 1ns/1ns
module vl_wb_adr_inc ( cyc_i, stb_i, cti_i, bte_i, adr_i, ack_o, adr_o, clk, rst);
module vl_wb_adr_inc ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
parameter adr_width = 10;
parameter adr_width = 10;
parameter max_burst_width = 4;
parameter max_burst_width = 4;
input cyc_i, stb_i;
input cyc_i, stb_i, we_i;
input [2:0] cti_i;
input [2:0] cti_i;
input [1:0] bte_i;
input [1:0] bte_i;
input [adr_width-1:0] adr_i;
input [adr_width-1:0] adr_i;
output [adr_width-1:0] adr_o;
output [adr_width-1:0] adr_o;
output ack_o;
output ack_o;
Line 2071... Line 2086...
        last_cycle <= (!cyc_i) ? idle :
        last_cycle <= (!cyc_i) ? idle :
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? eoc :
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? eoc :
                      (cyc_i & !stb_i) ? ws :
                      (cyc_i & !stb_i) ? ws :
                      cyc;
                      cyc;
    assign to_adr = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
    assign to_adr = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
    assign adr_o[max_burst_width-1:0] = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
 
                                        (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] :
 
                                        adr[max_burst_width-1:0];
    assign ack_o = last_cycle == cyc;
    assign ack_o = last_cycle == cyc;
end
end
endgenerate
endgenerate
generate
generate
if (max_burst_width==2) begin : inst_2
if (max_burst_width==2) begin : inst_2
Line 2316... Line 2333...
module vl_wb3avalon_bridge (
module vl_wb3avalon_bridge (
        // wishbone slave side
        // wishbone slave side
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
        // avalon master side
        // avalon master side
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
 
parameter linewrapburst = 1'b0;
input [31:0] wbs_dat_i;
input [31:0] wbs_dat_i;
input [31:2] wbs_adr_i;
input [31:2] wbs_adr_i;
input [3:0]  wbs_sel_i;
input [3:0]  wbs_sel_i;
input [1:0]  wbs_bte_i;
input [1:0]  wbs_bte_i;
input [2:0]  wbs_cti_i;
input [2:0]  wbs_cti_i;
Line 2371... Line 2389...
if (rst) begin
if (rst) begin
    counter <= 4'd0;
    counter <= 4'd0;
end else
end else
    if (wbm_we_o) begin
    if (wbm_we_o) begin
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
            counter <= burstcount -1;
            counter <= burstcount -4'd1;
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
            counter <= burstcount;
            counter <= burstcount;
        end else if (!waitrequest & wbm_stb_o) begin
        end else if (!waitrequest & wbm_stb_o) begin
            counter <= counter - 4'd1;
            counter <= counter - 4'd1;
        end
        end
Line 2640... Line 2658...
// WB RAM with byte enable
// WB RAM with byte enable
module vl_wb_b3_ram_be (
module vl_wb_b3_ram_be (
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
    wbs_dat_o, wbs_ack_o, wb_clk, wb_rst);
    wbs_dat_o, wbs_ack_o, wb_clk, wb_rst);
parameter adr_size = 16;
parameter adr_size = 16;
parameter adr_lo   = 2;
parameter mem_size = 1<<adr_size;
parameter mem_size = 1<<16;
 
parameter dat_size = 32;
parameter dat_size = 32;
parameter max_burst_width = 4;
parameter max_burst_width = 4;
parameter memory_init = 1;
parameter memory_init = 1;
parameter memory_file = "vl_ram.vmem";
parameter memory_file = "vl_ram.vmem";
localparam aw = (adr_size - adr_lo);
localparam aw = (adr_size);
localparam dw = dat_size;
localparam dw = dat_size;
localparam sw = dat_size/8;
localparam sw = dat_size/8;
localparam cw = 3;
localparam cw = 3;
localparam bw = 2;
localparam bw = 2;
input [dw-1:0] wbs_dat_i;
input [dw-1:0] wbs_dat_i;
Line 2660... Line 2677...
input [sw-1:0] wbs_sel_i;
input [sw-1:0] wbs_sel_i;
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
output [dw-1:0] wbs_dat_o;
output [dw-1:0] wbs_dat_o;
output wbs_ack_o;
output wbs_ack_o;
input wb_clk, wb_rst;
input wb_clk, wb_rst;
reg wbs_ack_o;
 
wire [aw-1:0] adr;
wire [aw-1:0] adr;
vl_ram_be # (
vl_ram_be # (
    .data_width(dat_size),
    .data_width(dat_size),
    .addr_width(aw),
    .addr_width(aw),
    .mem_size(mem_size),
    .mem_size(mem_size),
Line 2672... Line 2688...
    .memory_file(memory_file))
    .memory_file(memory_file))
ram0(
ram0(
    .d(wbs_dat_i),
    .d(wbs_dat_i),
    .adr(adr),
    .adr(adr),
    .be(wbs_sel_i),
    .be(wbs_sel_i),
    .we(wbs_we_i),
    .we(wbs_we_i & wb_ack_o),
    .q(wbs_dat_o),
    .q(wbs_dat_o),
    .clk(wb_clk)
    .clk(wb_clk)
);
);
vl_wb_adr_inc # ( .adr_width(aw), .max_burst_width(max_burst_width)) adr_inc0 (
vl_wb_adr_inc # ( .adr_width(aw), .max_burst_width(max_burst_width)) adr_inc0 (
    .cyc_i(wbs_cyc_i),
    .cyc_i(wbs_cyc_i),
    .stb_i(wbs_stb_i),
    .stb_i(wbs_stb_i),
    .cti_i(wbs_cti_i),
    .cti_i(wbs_cti_i),
    .bte_i(wbs_bte_i),
    .bte_i(wbs_bte_i),
    .adr_i(wbs_adr_i),
    .adr_i(wbs_adr_i),
 
    .we_i(wbs_we_i),
    .ack_o(wbs_ack_o),
    .ack_o(wbs_ack_o),
    .adr_o(adr),
    .adr_o(adr),
    .clk(wb_clk),
    .clk(wb_clk),
    .rst(wb_rst));
    .rst(wb_rst));
endmodule
endmodule

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