| Line 1428... |
Line 1428... |
input [(data_width/8)-1:0] be;
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input [(data_width/8)-1:0] be;
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input we;
|
input we;
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output reg [(data_width-1):0] q;
|
output reg [(data_width-1):0] q;
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input clk;
|
input clk;
|
`ifdef SYSTEMVERILOG
|
`ifdef SYSTEMVERILOG
|
|
// use a multi-dimensional packed array
|
|
//t o model individual bytes within the word
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logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
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logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
|
`else
|
`else
|
reg [data_width-1:0] ram [mem_size-1:0];
|
reg [data_width-1:0] ram [mem_size-1:0];
|
wire [data_width/8-1:0] cke;
|
wire [data_width/8-1:0] cke;
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`endif
|
`endif
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| Line 1443... |
Line 1445... |
$readmemh(memory_file, ram);
|
$readmemh(memory_file, ram);
|
end
|
end
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end
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end
|
endgenerate
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endgenerate
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`ifdef SYSTEMVERILOG
|
`ifdef SYSTEMVERILOG
|
// use a multi-dimensional packed array
|
|
//to model individual bytes within the word
|
|
always_ff@(posedge clk)
|
always_ff@(posedge clk)
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begin
|
begin
|
if(we) begin // note: we should have a for statement to support any bus width
|
if(we) begin
|
if(be[3]) ram[adr][3] <= d[31:24];
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if(be[3]) ram[adr][3] <= d[31:24];
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if(be[2]) ram[adr][2] <= d[23:16];
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if(be[2]) ram[adr][2] <= d[23:16];
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if(be[1]) ram[adr][1] <= d[15:8];
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if(be[1]) ram[adr][1] <= d[15:8];
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if(be[0]) ram[adr][0] <= d[7:0];
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if(be[0]) ram[adr][0] <= d[7:0];
|
end
|
end
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| Line 1582... |
Line 1582... |
end
|
end
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endmodule
|
endmodule
|
module vl_dpram_be_2r2w ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
|
module vl_dpram_be_2r2w ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
|
parameter a_data_width = 32;
|
parameter a_data_width = 32;
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parameter a_addr_width = 8;
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parameter a_addr_width = 8;
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parameter b_data_width = a_data_width;
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parameter b_data_width = 64; //a_data_width;
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localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
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localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
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parameter mem_size = (a_addr_width>b_addr_width) ? (1<<a_addr_width) : (1<<b_addr_width);
|
localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
|
|
parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
|
|
parameter init = 0;
|
|
parameter memory_file = "vl_ram.vmem";
|
input [(a_data_width-1):0] d_a;
|
input [(a_data_width-1):0] d_a;
|
input [(a_addr_width-1):0] adr_a;
|
input [(a_addr_width-1):0] adr_a;
|
input [(a_data_width/8-1):0] be_a;
|
input [(a_data_width/8-1):0] be_a;
|
input we_a;
|
input we_a;
|
output reg [(a_data_width-1):0] q_a;
|
output reg [(a_data_width-1):0] q_a;
|
| Line 1601... |
Line 1604... |
`ifdef SYSTEMVERILOG
|
`ifdef SYSTEMVERILOG
|
// use a multi-dimensional packed array
|
// use a multi-dimensional packed array
|
//to model individual bytes within the word
|
//to model individual bytes within the word
|
generate
|
generate
|
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
|
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
|
logic [3:0][7:0] ram [0:mem_size-1];
|
logic [0:3][7:0] ram [0:mem_size-1];
|
|
initial
|
|
if (init)
|
|
$readmemh(memory_file, ram);
|
always_ff@(posedge clk_a)
|
always_ff@(posedge clk_a)
|
begin
|
begin
|
if(we_a) begin
|
if(we_a) begin
|
if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
|
if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
|
if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
|
if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
|
| Line 1626... |
Line 1632... |
end
|
end
|
always@(posedge clk_b)
|
always@(posedge clk_b)
|
q_b = ram[adr_b];
|
q_b = ram[adr_b];
|
end
|
end
|
endgenerate
|
endgenerate
|
|
generate
|
|
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
|
|
logic [0:7][7:0] ram [0:mem_size-1];
|
|
initial
|
|
if (init)
|
|
$readmemh(memory_file, ram);
|
|
always_ff@(posedge clk_a)
|
|
begin
|
|
if(we_a) begin
|
|
if(be_a[7]) ram[adr_a][7] <= d_a[63:56];
|
|
if(be_a[6]) ram[adr_a][6] <= d_a[55:48];
|
|
if(be_a[5]) ram[adr_a][5] <= d_a[47:40];
|
|
if(be_a[4]) ram[adr_a][4] <= d_a[39:32];
|
|
if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
|
|
if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
|
|
if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
|
|
if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
|
|
end
|
|
end
|
|
always@(posedge clk_a)
|
|
q_a = ram[adr_a];
|
|
always_ff@(posedge clk_b)
|
|
begin
|
|
if(we_b) begin
|
|
if(be_b[7]) ram[adr_b][7] <= d_b[63:56];
|
|
if(be_b[6]) ram[adr_b][6] <= d_b[55:48];
|
|
if(be_b[5]) ram[adr_b][5] <= d_b[47:40];
|
|
if(be_b[4]) ram[adr_b][4] <= d_b[39:32];
|
|
if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
|
|
if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
|
|
if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
|
|
if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
|
|
end
|
|
end
|
|
always@(posedge clk_b)
|
|
q_b = ram[adr_b];
|
|
end
|
|
endgenerate
|
|
generate
|
|
if (a_data_width==32 & b_data_width==16) begin : dpram_3216
|
|
logic [31:0] temp;
|
|
vl_dpram_be_2r2w # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(init), .memory_file(memory_file))
|
|
dpram6464 (
|
|
.d_a(d_a),
|
|
.q_a(q_a),
|
|
.adr_a(adr_a),
|
|
.be_a(be_a),
|
|
.we_a(we_a),
|
|
.clk_a(clk_a),
|
|
.d_b({d_b,d_b}),
|
|
.q_b(temp),
|
|
.adr_b(adr_b),
|
|
.be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}),
|
|
.we_b(we_b),
|
|
.clk_b(clk_b)
|
|
);
|
|
always_comb
|
|
if (adr_b[0])
|
|
q_b = temp[31:16];
|
|
else
|
|
q_b = temp[15:0];
|
|
end
|
|
endgenerate
|
|
generate
|
|
if (a_data_width==32 & b_data_width==64) begin : dpram_3264
|
|
logic [63:0] temp;
|
|
vl_dpram_be_2r2w # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(init), .memory_file(memory_file))
|
|
dpram6464 (
|
|
.d_a({d_a,d_a}),
|
|
.q_a(temp),
|
|
.adr_a(adr_a[a_addr_width-1:1]),
|
|
.be_a({be_a,be_a} & {{4{adr_a[0]}},{4{!adr_a[0]}}}),
|
|
.we_a(we_a),
|
|
.clk_a(clk_a),
|
|
.d_b(d_b),
|
|
.q_b(q_b),
|
|
.adr_b(adr_b),
|
|
.be_b(be_b),
|
|
.we_b(we_b),
|
|
.clk_b(clk_b)
|
|
);
|
|
always_comb
|
|
if (adr_a[0])
|
|
q_a = temp[63:32];
|
|
else
|
|
q_a = temp[31:0];
|
|
end
|
|
endgenerate
|
`else
|
`else
|
// This modules requires SystemVerilog
|
// This modules requires SystemVerilog
|
`endif
|
`endif
|
endmodule
|
endmodule
|
// FIFO
|
// FIFO
|
| Line 2104... |
Line 2198... |
module vl_wb3wb3_bridge (
|
module vl_wb3wb3_bridge (
|
// wishbone slave side
|
// wishbone slave side
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
|
// wishbone master side
|
// wishbone master side
|
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
|
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
|
|
parameter style = "FIFO"; // valid: simple, FIFO
|
|
parameter addr_width = 4;
|
input [31:0] wbs_dat_i;
|
input [31:0] wbs_dat_i;
|
input [31:2] wbs_adr_i;
|
input [31:2] wbs_adr_i;
|
input [3:0] wbs_sel_i;
|
input [3:0] wbs_sel_i;
|
input [1:0] wbs_bte_i;
|
input [1:0] wbs_bte_i;
|
input [2:0] wbs_cti_i;
|
input [2:0] wbs_cti_i;
|
| Line 2124... |
Line 2220... |
output wbm_cyc_o;
|
output wbm_cyc_o;
|
output wbm_stb_o;
|
output wbm_stb_o;
|
input [31:0] wbm_dat_i;
|
input [31:0] wbm_dat_i;
|
input wbm_ack_i;
|
input wbm_ack_i;
|
input wbm_clk, wbm_rst;
|
input wbm_clk, wbm_rst;
|
parameter addr_width = 4;
|
|
// bte
|
// bte
|
parameter linear = 2'b00;
|
parameter linear = 2'b00;
|
parameter wrap4 = 2'b01;
|
parameter wrap4 = 2'b01;
|
parameter wrap8 = 2'b10;
|
parameter wrap8 = 2'b10;
|
parameter wrap16 = 2'b11;
|
parameter wrap16 = 2'b11;
|
// cti
|
// cti
|
parameter classic = 3'b000;
|
parameter classic = 3'b000;
|
parameter incburst = 3'b010;
|
parameter incburst = 3'b010;
|
parameter endofburst = 3'b111;
|
parameter endofburst = 3'b111;
|
parameter wbs_adr = 1'b0;
|
localparam wbs_adr = 1'b0;
|
parameter wbs_data = 1'b1;
|
localparam wbs_data = 1'b1;
|
parameter wbm_adr0 = 2'b00;
|
localparam wbm_adr0 = 2'b00;
|
parameter wbm_adr1 = 2'b01;
|
localparam wbm_adr1 = 2'b01;
|
parameter wbm_data = 2'b10;
|
localparam wbm_data = 2'b10;
|
parameter wbm_data_wait = 2'b11;
|
localparam wbm_data_wait = 2'b11;
|
reg [1:0] wbs_bte_reg;
|
reg [1:0] wbs_bte_reg;
|
reg wbs;
|
reg wbs;
|
wire wbs_eoc_alert, wbm_eoc_alert;
|
wire wbs_eoc_alert, wbm_eoc_alert;
|
reg wbs_eoc, wbm_eoc;
|
reg wbs_eoc, wbm_eoc;
|
reg [1:0] wbm;
|
reg [1:0] wbm;
|
