Line 39... |
Line 39... |
//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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`ifdef WB_ADR_INC
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`ifdef WB_ADR_INC
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// async wb3 - wb3 bridge
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`timescale 1ns/1ns
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`timescale 1ns/1ns
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`define MODULE wb_adr_inc
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`define MODULE wb_adr_inc
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module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
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module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
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`undef MODULE
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`undef MODULE
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parameter adr_width = 10;
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parameter adr_width = 10;
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Line 879... |
Line 878... |
wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
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wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
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wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
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wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
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|
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parameter dat_width = 32;
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parameter dat_width = 32;
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parameter adr_width = 8;
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parameter adr_width = 8;
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parameter mem_size = 1<<adr_width;
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parameter memory_init = 0;
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parameter memory_file = "vl_ram.v";
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parameter debug = 0;
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|
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input [dat_width-1:0] wb_dat_i;
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input [dat_width-1:0] wb_dat_i;
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input [adr_width-1:0] wb_adr_i;
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input [adr_width-1:0] wb_adr_i;
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input [dat_width/8-1:0] wb_sel_i;
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input [dat_width/8-1:0] wb_sel_i;
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input wb_we_i, wb_stb_i, wb_cyc_i;
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input wb_we_i, wb_stb_i, wb_cyc_i;
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output [dat_width-1:0] wb_dat_o;
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output [dat_width-1:0] wb_dat_o;
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reg [dat_width-1:0] wb_dat_o;
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output wb_stall_o;
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output wb_stall_o;
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output wb_ack_o;
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output wb_ack_o;
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reg wb_ack_o;
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reg wb_ack_o;
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input wb_clk, wb_rst;
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input wb_clk, wb_rst;
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|
|
wire [dat_width/8-1:0] cke;
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wire [dat_width/8-1:0] cke;
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|
|
generate
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`define MODULE ram_be
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if (dat_width==32) begin
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`BASE`MODULE # (
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reg [7:0] ram3 [1<<(adr_width-2)-1:0];
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.data_width(dat_width),
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reg [7:0] ram2 [1<<(adr_width-2)-1:0];
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.addr_width(adr_width),
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reg [7:0] ram1 [1<<(adr_width-2)-1:0];
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.mem_size(mem_size),
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reg [7:0] ram0 [1<<(adr_width-2)-1:0];
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.memory_init(memory_init),
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assign cke = wb_sel_i & {(dat_width/8){wb_we_i}};
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.memory_file(memory_file))
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always @ (posedge wb_clk)
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ram0(
|
begin
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`undef MODULE
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if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
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.d(wb_dat_i),
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if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
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.adr(wb_adr_i),
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if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
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.be(wb_sel_i),
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if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
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.we(wb_we_i & wb_stb_i & wb_cyc_i),
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end
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.q(wb_dat_o),
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always @ (posedge wb_clk or posedge wb_rst)
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.clk(wb_clk)
|
begin
|
);
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if (wb_rst)
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|
wb_dat_o <= 32'h0;
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else
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wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
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end
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end
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endgenerate
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|
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always @ (posedge wb_clk or posedge wb_rst)
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always @ (posedge wb_clk or posedge wb_rst)
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if (wb_rst)
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if (wb_rst)
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wb_ack_o <= 1'b0;
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wb_ack_o <= 1'b0;
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else
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else
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Line 1148... |
Line 1143... |
`undef MODULE
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`undef MODULE
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|
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parameter dw_s = 32;
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parameter dw_s = 32;
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parameter aw_s = 24;
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parameter aw_s = 24;
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parameter dw_m = dw_s;
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parameter dw_m = dw_s;
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parameter aw_m = dw_s * aw_s / dw_m;
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localparam aw_m = dw_s * aw_s / dw_m;
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parameter max_burst_width = 4;
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parameter wbs_max_burst_width = 4;
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|
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parameter async = 1; // wbs_clk != wbm_clk
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parameter async = 1; // wbs_clk != wbm_clk
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|
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parameter nr_of_ways = 1;
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parameter nr_of_ways = 1;
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parameter aw_offset = 4; // 4 => 16 words per cache line
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parameter aw_offset = 4; // 4 => 16 words per cache line
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parameter aw_slot = 10;
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parameter aw_slot = 10;
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|
|
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parameter valid_mem = 0;
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parameter debug = 0;
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|
|
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localparam aw_b_offset = aw_offset * dw_s / dw_m;
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localparam aw_tag = aw_s - aw_slot - aw_offset;
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localparam aw_tag = aw_s - aw_slot - aw_offset;
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parameter wbm_burst_size = 4; // valid options 4,8,16
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parameter wbm_burst_size = 4; // valid options 4,8,16
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localparam bte = (wbm_burst_size==4) ? 2'b01 : (wbm_burst_size==8) ? 2'b10 : 2'b11;
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localparam bte = (wbm_burst_size==4) ? 2'b01 : (wbm_burst_size==8) ? 2'b10 : 2'b11;
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`define SIZE2WIDTH wbm_burst_size
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`define SIZE2WIDTH wbm_burst_size
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localparam wbm_burst_width `SIZE2WIDTH_EXPR
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localparam wbm_burst_width `SIZE2WIDTH_EXPR
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`undef SIZE2WIDTH
|
`undef SIZE2WIDTH
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localparam nr_of_wbm_burst = ((1<<aw_offset)/wbm_burst_size) * dw_s / dw_m;
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localparam nr_of_wbm_burst = ((1<<aw_offset)/wbm_burst_size) * dw_s / dw_m;
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`define SIZE2WIDTH nr_of_wbm_burst
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`define SIZE2WIDTH nr_of_wbm_burst
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localparam nr_of_wbm_burst_width `SIZE2WIDTH_EXPR
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localparam nr_of_wbm_burst_width `SIZE2WIDTH_EXPR
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`undef SIZE2WIDTH
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`undef SIZE2WIDTH
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input [dw_s-1:0] wbs_dat_i;
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input [dw_s-1:0] wbs_dat_i;
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input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
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input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
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input [dw_s/8-1:0] wbs_sel_i;
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input [dw_s/8-1:0] wbs_sel_i;
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input [2:0] wbs_cti_i;
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input [2:0] wbs_cti_i;
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input [1:0] wbs_bte_i;
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input [1:0] wbs_bte_i;
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Line 1187... |
Line 1188... |
input [dw_m-1:0] wbm_dat_i;
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input [dw_m-1:0] wbm_dat_i;
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input wbm_ack_i;
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input wbm_ack_i;
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input wbm_stall_i;
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input wbm_stall_i;
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input wbm_clk, wbm_rst;
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input wbm_clk, wbm_rst;
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|
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wire dirty, valid;
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wire valid, dirty, hit;
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wire [aw_tag-1:0] tag;
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wire [aw_tag-1:0] tag;
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wire tag_mem_we;
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wire tag_mem_we;
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wire [aw_tag-1:0] wbs_adr_tag;
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wire [aw_tag-1:0] wbs_adr_tag;
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wire [aw_slot-1:0] wbs_adr_slot;
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wire [aw_slot-1:0] wbs_adr_slot;
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wire [aw_offset-1:0] wbs_adr_word;
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wire [aw_offset-1:0] wbs_adr_word;
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Line 1208... |
Line 1209... |
wire done, mem_alert, mem_done;
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wire done, mem_alert, mem_done;
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|
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// wbm side
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// wbm side
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reg [aw_m-1:0] wbm_radr;
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reg [aw_m-1:0] wbm_radr;
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reg [aw_m-1:0] wbm_wadr;
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reg [aw_m-1:0] wbm_wadr;
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wire [aw_slot+-1:0] wbm_adr;
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wire [aw_slot-1:0] wbm_adr;
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wire wbm_radr_cke, wbm_wadr_cke;
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wire wbm_radr_cke, wbm_wadr_cke;
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reg [1:0] phase;
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reg [2:0] phase;
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localparam wbm_wait = 2'b00;
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// phase = {we,stb,cyc}
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localparam wbm_rd = 2'b10;
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localparam wbm_wait = 3'b000;
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localparam wbm_wr = 2'b11;
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localparam wbm_wr = 3'b111;
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localparam wbm_wr_drain = 3'b101;
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localparam wbm_rd = 3'b011;
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localparam wbm_rd_drain = 3'b001;
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assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
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assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
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assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
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assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
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|
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`define MODULE ram
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generate
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if (valid_mem==0) begin : no_valid_mem
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assign valid = 1'b1;
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end else begin : valid_mem_inst
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`define MODULE dpram_1r1w
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`BASE`MODULE
|
`BASE`MODULE
|
# ( .data_width(aw_tag), .addr_width(aw_slot))
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# ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
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tag_mem ( .d(wbs_adr_slot), .adr(wbs_adr_tag), .we(done), .q(tag), .clk(wbs_clk));
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valid_mem ( .d_a(1'b1), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
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.q_b(valid), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
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`undef MODULE
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|
end
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|
endgenerate
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|
|
|
`define MODULE dpram_1r1w
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|
`BASE`MODULE
|
|
# ( .data_width(aw_tag), .addr_width(aw_slot), .memory_init(2), .debug(debug))
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tag_mem ( .d_a(wbs_adr_tag), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
|
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.q_b(tag), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
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assign hit = wbs_adr_tag == tag;
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`undef MODULE
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|
|
|
`define MODULE dpram_1r2w
|
|
`BASE`MODULE
|
|
# ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
|
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dirty_mem (
|
|
.d_a(1'b1), .q_a(dirty), .adr_a(wbs_adr_slot), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .clk_a(wbs_clk),
|
|
.d_b(1'b0), .adr_b(wbs_adr_slot), .we_b(mem_done), .clk_b(wbm_clk));
|
`undef MODULE
|
`undef MODULE
|
assign valid = wbs_adr_tag == tag;
|
|
|
|
`define MODULE wb_adr_inc
|
`define MODULE wb_adr_inc
|
`BASE`MODULE # ( .adr_width(aw_s), .max_burst_width(max_burst_width)) adr_inc0 (
|
`BASE`MODULE # ( .adr_width(aw_s), .max_burst_width(wbs_max_burst_width)) adr_inc0 (
|
.cyc_i(wbs_cyc_i),
|
.cyc_i(wbs_cyc_i & (state==rdwr) & hit & valid),
|
.stb_i(wbs_stb_i & (state==idle | (state==rw & valid))), // throttle depending on valid
|
.stb_i(wbs_stb_i & (state==rdwr) & hit & valid), // throttle depending on valid
|
.cti_i(wbs_cti_i),
|
.cti_i(wbs_cti_i),
|
.bte_i(wbs_bte_i),
|
.bte_i(wbs_bte_i),
|
.adr_i(wbs_adr_i),
|
.adr_i(wbs_adr_i),
|
.we_i (wbs_we_i),
|
.we_i (wbs_we_i),
|
.ack_o(wbs_ack_o),
|
.ack_o(wbs_ack_o),
|
.adr_o(wbs_adr),
|
.adr_o(wbs_adr),
|
.clk(wbsa_clk),
|
.clk(wbs_clk),
|
.rst(wbsa_rst));
|
.rst(wbs_rst));
|
`undef MODULE
|
`undef MODULE
|
|
|
`define MODULE dpram_be_2r2w
|
`define MODULE dpram_be_2r2w
|
`BASE`MODULE
|
`BASE`MODULE
|
# ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m) )
|
# ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m), .debug(debug))
|
cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]), .be_a(wbs_sel_i), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .q_a(wbs_dat_o), .clk_a(wbs_clk),
|
cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]), .be_a(wbs_sel_i), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .q_a(wbs_dat_o), .clk_a(wbs_clk),
|
.d_b(wbm_dat_i), .adr_b(wbm_adr), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
|
.d_b(wbm_dat_i), .adr_b(wbm_adr_o[aw_slot+aw_offset-1:0]), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
|
|
// .d_b(wbm_dat_i), .adr_b(wbm_adr), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
|
`undef MODULE
|
`undef MODULE
|
|
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
if (wbs_rst)
|
if (wbs_rst)
|
state <= idle;
|
state <= idle;
|
Line 1256... |
Line 1283... |
case (state)
|
case (state)
|
idle:
|
idle:
|
if (wbs_cyc_i)
|
if (wbs_cyc_i)
|
state <= rdwr;
|
state <= rdwr;
|
rdwr:
|
rdwr:
|
if (wbs_we_i & valid & eoc)
|
casex ({valid, hit, dirty, eoc})
|
state <= idle;
|
4'b0xxx: state <= pull;
|
else if (wbs_we_i & !valid)
|
4'b11x1: state <= idle;
|
state <= pull;
|
4'b101x: state <= push;
|
else if (!wbs_we_i & valid & eoc)
|
4'b100x: state <= pull;
|
state <= idle;
|
endcase
|
else if (!wbs_we_i & !valid & !dirty)
|
|
state <= pull;
|
|
else if (!wbs_we_i & !valid & dirty)
|
|
state <= push;
|
|
push:
|
push:
|
if (done)
|
if (done)
|
state <= rdwr;
|
state <= rdwr;
|
pull:
|
pull:
|
if (done)
|
if (done)
|
state <= rdwr;
|
state <= rdwr;
|
default: state <= idle;
|
default: state <= idle;
|
endcase
|
endcase
|
|
|
|
|
// cdc
|
// cdc
|
generate
|
generate
|
if (async==1) begin : cdc0
|
if (async==1) begin : cdc0
|
`define MODULE cdc
|
`define MODULE cdc
|
`BASE`MODULE cdc0 ( .start_pl(state==rdwr & !valid), .take_it_pl(mem_alert), .take_it_grant_pl(mem_done), .got_it_pl(done), .clk_src(wbs_clk), .rst_src(wbs_rst), .clk_dst(wbm_clk), .rst_dst(wbm_rst));
|
`BASE`MODULE cdc0 ( .start_pl(state==rdwr & (!valid | !hit)), .take_it_pl(mem_alert), .take_it_grant_pl(mem_done), .got_it_pl(done), .clk_src(wbs_clk), .rst_src(wbs_rst), .clk_dst(wbm_clk), .rst_dst(wbm_rst));
|
`undef MODULE
|
`undef MODULE
|
end
|
end
|
else begin : nocdc
|
else begin : nocdc
|
assign mem_alert = state==rdwr & !valid;
|
assign mem_alert = state==rdwr & (!valid | !hit);
|
assign done = mem_done;
|
assign done = mem_done;
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
// FSM generating a number of burts 4 cycles
|
// FSM generating a number of burts 4 cycles
|
// actual number depends on data width ratio
|
// actual number depends on data width ratio
|
// nr_of_wbm_burst
|
// nr_of_wbm_burst
|
reg [nr_of_wbm_burst_width+wbm_burst_width-1:0] cnt0;
|
reg [wbm_burst_width-1:0] cnt_rw, cnt_ack;
|
reg [nr_of_wbm_burst_width+wbm_burst_width-1:0] cnt1;
|
|
|
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
if (wbm_rst)
|
if (wbm_rst)
|
cnt0 <= {nr_of_wbm_burst_width+wbm_burst_width{1'b0}};
|
cnt_rw <= {wbm_burst_width{1'b0}};
|
else
|
else
|
if (wbm_radr_cke)
|
if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i)
|
cnt0 <= cnt0 + 1;//(nr_of_wbm_burst_width+wbm_burst_width)1'd1;
|
cnt_rw <= cnt_rw + 1;
|
assign wbm_radr_cke = wbm_cyc_o & wbm_stb_o & !wbm_stall_i;
|
|
assign wbm_radr = {wbs_adr_tag, tag, cnt0};
|
|
|
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
if (wbm_rst)
|
if (wbm_rst)
|
cnt1 <= {nr_of_wbm_burst_width+wbm_burst_width{1'b0}};
|
cnt_ack <= {wbm_burst_width{1'b0}};
|
else
|
else
|
if (wbm_wadr_cke)
|
if (wbm_ack_i)
|
cnt1 <= cnt1 + 1;//(nr_of_wbm_burst_width+wbm_burst_width)1'd1;
|
cnt_ack <= cnt_ack + 1;
|
assign wbm_wadr_cke = wbm_ack_i;
|
|
assign wbm_wadr = {wbs_adr_tag, wbs_adr_slot, cnt1};
|
generate
|
|
if (nr_of_wbm_burst_width==0) begin : one_burst
|
|
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
if (wbm_rst)
|
if (wbm_rst)
|
phase <= wbm_wait;
|
phase <= wbm_wait;
|
else
|
else
|
case (phase)
|
case (phase)
|
wbm_wait:
|
wbm_wait:
|
if (mem_alert)
|
if (mem_alert)
|
phase <= state;
|
if (state==push)
|
|
phase <= wbm_wr;
|
|
else
|
|
phase <= wbm_rd;
|
wbm_wr:
|
wbm_wr:
|
if (&cnt1 & wbm_ack_i)
|
if (&cnt_rw)
|
|
phase <= wbm_wr_drain;
|
|
wbm_wr_drain:
|
|
if (&cnt_ack)
|
phase <= wbm_rd;
|
phase <= wbm_rd;
|
wbm_rd:
|
wbm_rd:
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if (&cnt0 & wbm_ack_i)
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if (&cnt_rw)
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phase <= idle;
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phase <= wbm_rd_drain;
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wbm_rd_drain:
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if (&cnt_ack)
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phase <= wbm_wait;
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default: phase <= wbm_wait;
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default: phase <= wbm_wait;
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endcase
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endcase
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assign wbm_adr_o = (phase==wbm_wr) ? {tag, wbs_adr_slot, cnt1} : {wbs_adr_tag, wbs_adr_slot, cnt1};
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assign mem_done = phase==wbm_rd_drain & (&cnt_ack) & wbm_ack_i;
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assign wbm_adr = (phase==wbm_wr) ? {wbs_adr_slot, cnt1} : {wbs_adr_slot, cnt1};
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assign wbm_cti_o = (&cnt0 | &cnt1) ? 3'b111 : 3'b010;
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end else begin : multiple_burst
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reg [nr_of_wbm_burst_width-1:0] cnt_burst;
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end
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endgenerate
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assign wbm_adr_o = (phase[2]) ? {tag, wbs_adr_slot, cnt_rw} : {wbs_adr_tag, wbs_adr_slot, cnt_rw};
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assign wbm_adr = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_rw};
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assign wbm_sel_o = {dw_m/8{1'b1}};
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assign wbm_cti_o = (&cnt_rw | !wbm_stb_o) ? 3'b111 : 3'b010;
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assign wbm_bte_o = bte;
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assign wbm_bte_o = bte;
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assign wbm_we_o = phase==wbm_wr;
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assign {wbm_we_o, wbm_stb_o, wbm_cyc_o} = phase;
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endmodule
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endmodule
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`endif
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`endif
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No newline at end of file
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No newline at end of file
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