Line 881... |
Line 881... |
);
|
);
|
|
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
|
`ifdef WB_SHADOW_RAM
|
|
// A wishbone compliant RAM module that can be placed in front of other memory controllers
|
|
`define MODULE wb_shadow_ram
|
|
module `BASE`MODULE (
|
|
`undef MODULE
|
|
wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
|
|
wbs_dat_o, wbs_ack_o, wbs_stall_o,
|
|
wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
|
|
wbm_dat_i, wbm_ack_i, wbm_stall_i,
|
|
wb_clk, wb_rst);
|
|
|
|
parameter dat_width = 32;
|
|
parameter mode = "B4";
|
|
parameter max_burst_width = 4; // only used for B3
|
|
|
|
parameter shadow_mem_adr_width = 10;
|
|
parameter shadow_mem_size = 1024;
|
|
parameter shadow_mem_init = 2;
|
|
parameter shadow_mem_file = "vl_ram.v";
|
|
|
|
parameter main_mem_adr_width = 24;
|
|
|
|
input [dat_width-1:0] wbs_dat_i;
|
|
input [main_mem_adr_width-1:0] wbs_adr_i;
|
|
input [2:0] wbs_cti_i;
|
|
input [1:0] wbs_bte_i;
|
|
input [dat_width/8-1:0] wbs_sel_i;
|
|
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
|
|
output [dat_width-1:0] wbs_dat_o;
|
|
output wbs_ack_o;
|
|
output wbs_stall_o;
|
|
|
|
output [dat_width-1:0] wbm_dat_o;
|
|
output [main_mem_adr_width-1:0] wbm_adr_o;
|
|
output [2:0] wbm_cti_o;
|
|
output [1:0] wbm_bte_o;
|
|
output [dat_width/8-1:0] wbm_sel_o;
|
|
output wbm_we_o, wbm_stb_o, wbm_cyc_o;
|
|
input [dat_width-1:0] wbm_dat_i;
|
|
input wbm_ack_i, wbm_stall_i;
|
|
|
|
input wb_clk, wb_rst;
|
|
|
|
generate
|
|
if (shadow_mem_size>0) begin : shadow_ram_inst
|
|
|
|
wire cyc;
|
|
wire [dat_width-1:0] dat;
|
|
wire stall, ack;
|
|
|
|
assign cyc = wbs_cyc_i & (wbs_adr_i<=shadow_mem_size);
|
|
`define MODULE wb_ram
|
|
`BASE`MODULE # (
|
|
.dat_width(dat_width),
|
|
.adr_width(shadow_mem_adr_width),
|
|
.mem_size(shadow_mem_size),
|
|
.memory_init(shadow_mem_init),
|
|
.mode(mode))
|
|
shadow_mem0 (
|
|
.wbs_dat_i(wbs_dat_i),
|
|
.wbs_adr_i(wbs_adr_i[shadow_mem_adr_width-1:0]),
|
|
.wbs_sel_i(wbs_sel_i),
|
|
.wbs_we_i (wbs_we_i),
|
|
.wbs_bte_i(wbs_bte_i),
|
|
.wbs_cti_i(wbs_cti_i),
|
|
.wbs_stb_i(wbs_stb_i),
|
|
.wbs_cyc_i(cyc),
|
|
.wbs_dat_o(dat),
|
|
.wbs_stall_o(stall),
|
|
.wbs_ack_o(ack),
|
|
.wb_clk(wb_clk),
|
|
.wb_rst(wb_rst));
|
|
`undef MODULE
|
|
|
|
assign {wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o} =
|
|
{wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i};
|
|
assign wbm_cyc_o = wbs_cyc_i & (wbs_adr_i>shadow_mem_size);
|
|
|
|
assign wbs_dat_o = (dat & {dat_width{cyc}}) | (wbm_dat_i & {dat_width{wbm_cyc_o}});
|
|
assign wbs_ack_o = (ack & cyc) | (wbm_ack_i & wbm_cyc_o);
|
|
assign wbs_stall_o = (stall & cyc) | (wbm_stall_i & wbm_cyc_o);
|
|
|
|
end else begin : no_shadow_ram_inst
|
|
|
|
assign {wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o} =
|
|
{wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i};
|
|
assign {wbs_dat_o, wbs_ack_o, wbs_stall_o} = {wbm_dat_i, wbm_ack_i, wbm_stall_i};
|
|
|
|
end
|
|
endgenerate
|
|
|
|
endmodule
|
|
`endif
|
|
|
`ifdef WB_B4_ROM
|
`ifdef WB_B4_ROM
|
// WB ROM
|
// WB ROM
|
`define MODULE wb_b4_rom
|
`define MODULE wb_b4_rom
|
module `BASE`MODULE (
|
module `BASE`MODULE (
|
`undef MODULE
|
`undef MODULE
|
Line 1113... |
Line 1207... |
`endif
|
`endif
|
|
|
`ifdef WB_CACHE
|
`ifdef WB_CACHE
|
`define MODULE wb_cache
|
`define MODULE wb_cache
|
module `BASE`MODULE (
|
module `BASE`MODULE (
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_stall_o, wbs_clk, wbs_rst,
|
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
|
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
|
);
|
);
|
`undef MODULE
|
`undef MODULE
|
|
|
parameter dw_s = 32;
|
parameter dw_s = 32;
|
parameter aw_s = 24;
|
parameter aw_s = 24;
|
parameter dw_m = dw_s;
|
parameter dw_m = dw_s;
|
localparam aw_m = dw_s * aw_s / dw_m;
|
localparam aw_m = dw_s * aw_s / dw_m;
|
parameter wbs_max_burst_width = 4;
|
parameter wbs_max_burst_width = 4;
|
|
parameter wbs_mode = "B3";
|
|
|
parameter async = 1; // wbs_clk != wbm_clk
|
parameter async = 1; // wbs_clk != wbm_clk
|
|
|
parameter nr_of_ways = 1;
|
parameter nr_of_ways = 1;
|
parameter aw_offset = 4; // 4 => 16 words per cache line
|
parameter aw_offset = 4; // 4 => 16 words per cache line
|
Line 1153... |
Line 1248... |
input [2:0] wbs_cti_i;
|
input [2:0] wbs_cti_i;
|
input [1:0] wbs_bte_i;
|
input [1:0] wbs_bte_i;
|
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
|
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
|
output [dw_s-1:0] wbs_dat_o;
|
output [dw_s-1:0] wbs_dat_o;
|
output wbs_ack_o;
|
output wbs_ack_o;
|
|
output wbs_stall_o;
|
input wbs_clk, wbs_rst;
|
input wbs_clk, wbs_rst;
|
|
|
output [dw_m-1:0] wbm_dat_o;
|
output [dw_m-1:0] wbm_dat_o;
|
output [aw_m-1:0] wbm_adr_o;
|
output [aw_m-1:0] wbm_adr_o;
|
output [dw_m/8-1:0] wbm_sel_o;
|
output [dw_m/8-1:0] wbm_sel_o;
|
Line 1180... |
Line 1276... |
localparam idle = 2'h0;
|
localparam idle = 2'h0;
|
localparam rdwr = 2'h1;
|
localparam rdwr = 2'h1;
|
localparam push = 2'h2;
|
localparam push = 2'h2;
|
localparam pull = 2'h3;
|
localparam pull = 2'h3;
|
wire eoc;
|
wire eoc;
|
|
wire we;
|
|
|
// cdc
|
// cdc
|
wire done, mem_alert, mem_done;
|
wire done, mem_alert, mem_done;
|
|
|
// wbm side
|
// wbm side
|
Line 1199... |
Line 1296... |
localparam wbm_wr_drain = 3'b101;
|
localparam wbm_wr_drain = 3'b101;
|
localparam wbm_rd = 3'b011;
|
localparam wbm_rd = 3'b011;
|
localparam wbm_rd_drain = 3'b001;
|
localparam wbm_rd_drain = 3'b001;
|
|
|
assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
|
assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
|
assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
|
|
|
|
generate
|
generate
|
if (valid_mem==0) begin : no_valid_mem
|
if (valid_mem==0) begin : no_valid_mem
|
assign valid = 1'b1;
|
assign valid = 1'b1;
|
end else begin : valid_mem_inst
|
end else begin : valid_mem_inst
|
Line 1230... |
Line 1326... |
dirty_mem (
|
dirty_mem (
|
.d_a(1'b1), .q_a(dirty), .adr_a(wbs_adr_slot), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .clk_a(wbs_clk),
|
.d_a(1'b1), .q_a(dirty), .adr_a(wbs_adr_slot), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .clk_a(wbs_clk),
|
.d_b(1'b0), .adr_b(wbs_adr_slot), .we_b(mem_done), .clk_b(wbm_clk));
|
.d_b(1'b0), .adr_b(wbs_adr_slot), .we_b(mem_done), .clk_b(wbm_clk));
|
`undef MODULE
|
`undef MODULE
|
|
|
|
generate
|
|
if (wbs_mode=="B3") begin : inst_b3
|
`define MODULE wb_adr_inc
|
`define MODULE wb_adr_inc
|
`BASE`MODULE # ( .adr_width(aw_s), .max_burst_width(wbs_max_burst_width)) adr_inc0 (
|
`BASE`MODULE # ( .adr_width(aw_s), .max_burst_width(wbs_max_burst_width)) adr_inc0 (
|
.cyc_i(wbs_cyc_i & (state==rdwr) & hit & valid),
|
.cyc_i(wbs_cyc_i & (state==rdwr) & hit & valid),
|
.stb_i(wbs_stb_i & (state==rdwr) & hit & valid), // throttle depending on valid
|
.stb_i(wbs_stb_i & (state==rdwr) & hit & valid), // throttle depending on valid
|
.cti_i(wbs_cti_i),
|
.cti_i(wbs_cti_i),
|
Line 1243... |
Line 1341... |
.ack_o(wbs_ack_o),
|
.ack_o(wbs_ack_o),
|
.adr_o(wbs_adr),
|
.adr_o(wbs_adr),
|
.clk(wbs_clk),
|
.clk(wbs_clk),
|
.rst(wbs_rst));
|
.rst(wbs_rst));
|
`undef MODULE
|
`undef MODULE
|
|
assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
|
|
assign we = wbs_cyc_i & wbs_we_i & wbs_ack_o;
|
|
end else if (wbs_mode=="B4") begin : inst_b4
|
|
end
|
|
|
|
endgenerate
|
|
|
`define MODULE dpram_be_2r2w
|
`define MODULE dpram_be_2r2w
|
`BASE`MODULE
|
`BASE`MODULE
|
# ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m), .debug(debug))
|
# ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m), .debug(debug))
|
cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]), .be_a(wbs_sel_i), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .q_a(wbs_dat_o), .clk_a(wbs_clk),
|
cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]), .be_a(wbs_sel_i), .we_a(we), .q_a(wbs_dat_o), .clk_a(wbs_clk),
|
.d_b(wbm_dat_i), .adr_b(wbm_adr_o[aw_slot+aw_offset-1:0]), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
|
.d_b(wbm_dat_i), .adr_b(wbm_adr_o[aw_slot+aw_offset-1:0]), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
|
// .d_b(wbm_dat_i), .adr_b(wbm_adr), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
|
|
`undef MODULE
|
`undef MODULE
|
|
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
if (wbs_rst)
|
if (wbs_rst)
|
state <= idle;
|
state <= idle;
|
Line 1385... |
Line 1488... |
assign {wbm_we_o, wbm_stb_o, wbm_cyc_o} = phase;
|
assign {wbm_we_o, wbm_stb_o, wbm_cyc_o} = phase;
|
|
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
No newline at end of file
|
No newline at end of file
|
|
`ifdef WB_AVALON_BRIDGE
|
|
// Wishbone to avalon bridge supporting one type of burst transfer only
|
|
// intended use is together with cache above
|
|
// WB B4 -> pipelined avalon
|
|
`define MODULE wb_avalon_bridge
|
|
module `BASE`MODULE (
|
|
`undef MODULE
|
|
// wishbone slave side
|
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_stall_o,
|
|
// avalon master side
|
|
readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer,
|
|
// common
|
|
clk, rst);
|
|
|
|
parameter adr_width = 30;
|
|
parameter dat_width = 32;
|
|
parameter burst_size = 4;
|
|
|
|
input [dat_width-1:0] wbs_dat_i;
|
|
input [adr_width-1:0] wbs_adr_i;
|
|
input [dat_width/8-1:0] wbs_sel_i;
|
|
input [1:0] wbs_bte_i;
|
|
input [2:0] wbs_cti_i;
|
|
input wbs_we_i;
|
|
input wbs_cyc_i;
|
|
input wbs_stb_i;
|
|
output [dat_width:0] wbs_dat_o;
|
|
output wbs_ack_o;
|
|
output wbs_stall_o;
|
|
|
|
input [dat_width-1:0] readdata;
|
|
input readdatavalid;
|
|
output [dat_width-1:0] writedata;
|
|
output [adr_width-1:0] address;
|
|
output [dat_width/8-1:0] be;
|
|
output write;
|
|
output read;
|
|
output beginbursttransfer;
|
|
output [3:0] burstcount;
|
|
input waitrequest;
|
|
input clk, rst;
|
|
|
|
reg last_cyc_idle_or_eoc;
|
|
|
|
reg [3:0] cnt;
|
|
always @ (posedge clk or posedge rst)
|
|
if (rst)
|
|
cnt <= 4'h0;
|
|
else
|
|
if (beginbursttransfer & waitrequest)
|
|
cnt <= burst_size - 1;
|
|
else if (beginbursttransfer & !waitrequest)
|
|
cnt <= burst_size - 2;
|
|
else if (wbs_ack_o)
|
|
cnt <= cnt - 1;
|
|
|
|
reg wr_ack;
|
|
always @ (posedge clk or posedge rst)
|
|
if (rst)
|
|
wr_ack <= 1'b0;
|
|
else
|
|
wr_ack <= (wbs_we_i & wbs_cyc_i & wbs_stb_i & !wbs_stall_o);
|
|
|
|
// to avalon
|
|
assign writedata = wbs_dat_i;
|
|
assign address = wbs_adr_i;
|
|
assign be = wbs_sel_i;
|
|
assign write = cnt==(burst_size-1) & wbs_cyc_i & wbs_we_i;
|
|
assign read = cnt==(burst_size-1) & wbs_cyc_i & !wbs_we_i;
|
|
assign beginbursttransfer = cnt==4'h0 & wbs_cyc_i;
|
|
assign burstcount = burst_size;
|
|
|
|
// to wishbone
|
|
assign wbs_dat_o = readdata;
|
|
assign wbs_ack_o = wr_ack | readdatavalid;
|
|
assign wbs_stall_o = waitrequest;
|
|
|
|
endmodule
|
|
`endif
|
|
|
|
`ifdef WB_AVALON_MEM_CACHE
|
|
`define MODULE wb_avalon_mem_cache
|
|
module `BASE`MODULE (
|
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_stall_o, wbs_clk, wbs_rst,
|
|
readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst
|
|
);
|
|
`undef MODULE
|
|
|
|
// wishbone
|
|
parameter wb_dat_width = 32;
|
|
parameter wb_adr_width = 22;
|
|
parameter wb_max_burst_width = 4;
|
|
parameter wb_mode = "B4";
|
|
// avalon
|
|
parameter avalon_dat_width = 32;
|
|
localparam avalon_adr_width = wb_dat_width * wb_adr_width / avalon_dat_width;
|
|
parameter avalon_burst_size = 4;
|
|
// cache
|
|
parameter async = 1;
|
|
parameter nr_of_ways = 1;
|
|
parameter aw_offset = 4;
|
|
parameter aw_slot = 10;
|
|
parameter valid_mem = 1;
|
|
// shadow RAM
|
|
parameter shadow_ram = 0;
|
|
parameter shadow_ram_adr_width = 10;
|
|
parameter shadow_ram_size = 1024;
|
|
parameter shadow_ram_init = 2; // 0: no init, 1: from file, 2: with zero
|
|
parameter shadow_ram_file = "vl_ram.v";
|
|
|
|
input [wb_dat_width-1:0] wbs_dat_i;
|
|
input [wb_adr_width-1:0] wbs_adr_i; // dont include a1,a0
|
|
input [wb_dat_width/8-1:0] wbs_sel_i;
|
|
input [2:0] wbs_cti_i;
|
|
input [1:0] wbs_bte_i;
|
|
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
|
|
output [wb_dat_width-1:0] wbs_dat_o;
|
|
output wbs_ack_o;
|
|
output wbs_stall_o;
|
|
input wbs_clk, wbs_rst;
|
|
|
|
input [avalon_dat_width-1:0] readdata;
|
|
input readdatavalid;
|
|
output [avalon_dat_width-1:0] writedata;
|
|
output [avalon_adr_width-1:0] address;
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output [avalon_dat_width/8-1:0] be;
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output write;
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output read;
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output beginbursttransfer;
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output [3:0] burstcount;
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input waitrequest;
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input clk, rst;
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`define DAT_WIDTH wb_dat_width
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`define ADR_WIDTH wb_adr_width
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`define WB wb1
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`include "wb_wires.v"
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`define WB wb2
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`include "wb_wires.v"
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`undef DAT_WIDTH
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`undef ADR_WIDTH
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`define MODULE wb_shadow_ram
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`BASE`MODULE # ( .dat_width(wb_dat_width), .mode(wb_mode), .max_burst_width(wb_max_burst_width),
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.shadow_mem_adr_width(shadow_ram_adr_width), .shadow_mem_size(shadow_ram_adr_width), .shadow_mem_init(shadow_ram_init), .shadow_mem_file(shadow_ram_file),
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.main_mem_adr_width(wb_adr_width))
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shadow_ram0 (
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.wbs_dat_i(wbs_dat_i), .wbs_adr_i(wbs_adr_i), .wbs_cti_i(wbs_cti_i), .wbs_bte_i(wbs_bte_i), .wbs_sel_i(wbs_sel_i), .wbs_we_i(wbs_we_i), .wbs_stb_i(wbs_stb_i), .wbs_cyc_i(wbs_cyc_i),
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.wbs_dat_o(wbs_dat_o), .wbs_ack_o(wbs_ack_o), .wbs_stall_o(wbs_stall_o),
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.wbm_dat_o(wb1_dat_o), .wbm_adr_o(wb1_adr_o), .wbm_cti_o(wb1_cti_o), .wbm_bte_o(wb1_bte_o), .wbm_sel_o(wb1_sel_o), .wbm_we_o(wb1_we_o), .wbm_stb_o(wb1_stb_o), .wbm_cyc_o(wb1_cyc_o),
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.wbm_dat_i(wb1_dat_i), .wbm_ack_i(wb1_ack_i), .wbm_stall_i(wb1_stall_i),
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.wb_clk(wbs_clk), .wb_rst(wbs_rst));
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`undef MODULE
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`define MODULE wb_cache
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`BASE`MODULE
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# ( .dw_s(wb_dat_width), .aw_s(wb_adr_width), .dw_m(avalon_dat_width), .wbs_mode(wb_mode), .wbs_max_burst_width(wb_max_burst_width), .async(async), .nr_of_ways(nr_of_ways), .aw_offset(aw_offset), .aw_slot(aw_slot), .valid_mem(valid_mem))
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cache0 (
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.wbs_dat_i(wb1_dat_o), .wbs_adr_i(wb1_adr_o), .wbs_sel_i(wb1_sel_o), .wbs_cti_i(wb1_cti_o), .wbs_bte_i(wb1_bte_o), .wbs_we_i(wb1_we_o), .wbs_stb_i(wb1_stb_o), .wbs_cyc_i(wb1_cyc_o),
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.wbs_dat_o(wb1_dat_i), .wbs_ack_o(wb1_ack_i), .wbs_stall_o(wb1_stall_i), .wbs_clk(wbs_clk), .wbs_rst(wbs_rst),
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.wbm_dat_o(wb2_dat_o), .wbm_adr_o(wb2_adr_o), .wbm_sel_o(wb2_sel_o), .wbm_cti_o(wb2_cti_o), .wbm_bte_o(wb2_bte_o), .wbm_we_o(wb2_we_o), .wbm_stb_o(wb2_stb_o), .wbm_cyc_o(wb2_cyc_o),
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.wbm_dat_i(wb2_dat_i), .wbm_ack_i(wb2_ack_i), .wbm_stall_i(wb2_stall_i), .wbm_clk(clk), .wbm_rst(rst));
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`undef MODULE
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`define MODULE wb_avalon_bridge
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`BASE`MODULE # ( .adr_width(avalon_adr_width), .dat_width(avalon_dat_width), .burst_size(avalon_burst_size))
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bridge0 (
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// wishbone slave side
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.wbs_dat_i(wb2_dat_o), .wbs_adr_i(wb2_adr_o), .wbs_sel_i(wb2_sel_o), .wbs_bte_i(wb2_bte_o), .wbs_cti_i(wb2_cti_o), .wbs_we_i(wb2_we_o), .wbs_cyc_i(wb2_cyc_o), .wbs_stb_i(wb2_stb_o),
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.wbs_dat_o(wb2_dat_i), .wbs_ack_o(wb2_ack_i), .wbs_stall_o(wb2_stall_i),
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// avalon master side
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.readdata(readdata), .readdatavalid(readdatavalid), .address(address), .read(read), .be(be), .write(write), .burstcount(burstcount), .writedata(writedata), .waitrequest(waitrequest), .beginbursttransfer(beginbursttransfer),
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// common
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.clk(clk), .rst(rst));
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`undef MODULE
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endmodule
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`endif
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No newline at end of file
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No newline at end of file
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