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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [wb.v] - Diff between revs 107 and 109

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Rev 107 Rev 109
Line 1132... Line 1132...
localparam addr_width_b = data_width_a * addr_width_a / data_width_b;
localparam addr_width_b = data_width_a * addr_width_a / data_width_b;
parameter mem_size = (addr_width_a>addr_width_b) ? (1<<addr_width_a) : (1<<addr_width_b);
parameter mem_size = (addr_width_a>addr_width_b) ? (1<<addr_width_a) : (1<<addr_width_b);
parameter max_burst_width_a = 4;
parameter max_burst_width_a = 4;
parameter max_burst_width_b = max_burst_width_a;
parameter max_burst_width_b = max_burst_width_a;
parameter mode = "B3";
parameter mode = "B3";
 
parameter memory_init = 0;
 
parameter memory_file = "vl_ram.v";
input [data_width_a-1:0] wbsa_dat_i;
input [data_width_a-1:0] wbsa_dat_i;
input [addr_width_a-1:0] wbsa_adr_i;
input [addr_width_a-1:0] wbsa_adr_i;
input [data_width_a/8-1:0] wbsa_sel_i;
input [data_width_a/8-1:0] wbsa_sel_i;
input [2:0] wbsa_cti_i;
input [2:0] wbsa_cti_i;
input [1:0] wbsa_bte_i;
input [1:0] wbsa_bte_i;
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
output [data_width_a-1:0] wbsa_dat_o;
output [data_width_a-1:0] wbsa_dat_o;
output reg wbsa_ack_o;
output wbsa_ack_o;
output wbsa_stall_o;
output wbsa_stall_o;
input wbsa_clk, wbsa_rst;
input wbsa_clk, wbsa_rst;
 
 
input [data_width_b-1:0] wbsb_dat_i;
input [data_width_b-1:0] wbsb_dat_i;
input [addr_width_b-1:0] wbsb_adr_i;
input [addr_width_b-1:0] wbsb_adr_i;
input [data_width_b/8-1:0] wbsb_sel_i;
input [data_width_b/8-1:0] wbsb_sel_i;
input [2:0] wbsb_cti_i;
input [2:0] wbsb_cti_i;
input [1:0] wbsb_bte_i;
input [1:0] wbsb_bte_i;
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
output [data_width_b-1:0] wbsb_dat_o;
output [data_width_b-1:0] wbsb_dat_o;
output reg wbsb_ack_o;
output wbsb_ack_o;
output wbsb_stall_o;
output wbsb_stall_o;
input wbsb_clk, wbsb_rst;
input wbsb_clk, wbsb_rst;
 
 
wire [addr_width_a-1:0] adr_a;
wire [addr_width_a-1:0] adr_a;
wire [addr_width_b-1:0] adr_b;
wire [addr_width_b-1:0] adr_b;
Line 1186... Line 1188...
    .clk(wbsb_clk),
    .clk(wbsb_clk),
    .rst(wbsb_rst));
    .rst(wbsb_rst));
`undef MODULE
`undef MODULE
assign we_b = wbsb_we_i & wbsb_ack_o;
assign we_b = wbsb_we_i & wbsb_ack_o;
end else if (mode=="B4") begin : b4_inst
end else if (mode=="B4") begin : b4_inst
always @ (posedge wbsa_clk or posedge wbsa_rst)
`define MODULE dff
    if (wbsa_rst)
`BASE`MODULE dffacka ( .d(wbsa_stb_i & wbsa_cyc_i), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
        wbsa_ack_o <= 1'b0;
 
    else
 
        wbsa_ack_o <= wbsa_stb_i & wbsa_cyc_i;
 
assign wbsa_stall_o = 1'b0;
assign wbsa_stall_o = 1'b0;
assign we_a = wbsa_we_i & wbsa_cyc_i & wbsa_stb_i;
assign we_a = wbsa_we_i & wbsa_cyc_i & wbsa_stb_i;
always @ (posedge wbsb_clk or posedge wbsb_rst)
`BASE`MODULE dffackb ( .d(wbsb_stb_i & wbsb_cyc_i), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
    if (wbsb_rst)
`undef MODULE
        wbsb_ack_o <= 1'b0;
 
    else
 
        wbsb_ack_o <= wbsb_stb_i & wbsb_cyc_i;
 
assign wbsb_stall_o = 1'b0;
assign wbsb_stall_o = 1'b0;
assign we_b = wbsb_we_i & wbsb_cyc_i & wbsb_stb_i;
assign we_b = wbsb_we_i & wbsb_cyc_i & wbsb_stb_i;
end
end
endgenerate
endgenerate
 
 
`define MODULE dpram_be_2r2w
`define MODULE dpram_be_2r2w
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size))
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size),
 
                 .b_data_width(data_width_b), .b_addr_width(addr_width_b),
 
                 .memory_init(memory_init), .memory_file(memory_file))
`undef MODULE
`undef MODULE
ram_i (
ram_i (
    .d_a(wbsa_dat_i),
    .d_a(wbsa_dat_i),
    .q_a(wbsa_dat_o),
    .q_a(wbsa_dat_o),
    .adr_a(adr_a),
    .adr_a(adr_a),

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