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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [wb.v] - Diff between revs 109 and 110

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Rev 109 Rev 110
Line 1201... Line 1201...
end
end
endgenerate
endgenerate
 
 
`define MODULE dpram_be_2r2w
`define MODULE dpram_be_2r2w
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size),
`BASE`MODULE # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size),
                 .b_data_width(data_width_b), .b_addr_width(addr_width_b),
                 .b_data_width(data_width_b),
                 .memory_init(memory_init), .memory_file(memory_file))
                 .memory_init(memory_init), .memory_file(memory_file))
`undef MODULE
`undef MODULE
ram_i (
ram_i (
    .d_a(wbsa_dat_i),
    .d_a(wbsa_dat_i),
    .q_a(wbsa_dat_o),
    .q_a(wbsa_dat_o),

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