Line 1540... |
Line 1540... |
`undef MODULE
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`undef MODULE
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// wishbone slave side
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// wishbone slave side
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wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_stall_o,
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wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_stall_o,
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// avalon master side
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// avalon master side
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readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer,
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readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer,
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init_done,
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// common
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// common
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clk, rst);
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clk, rst);
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parameter adr_width = 30;
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parameter adr_width = 30;
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parameter dat_width = 32;
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parameter dat_width = 32;
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Line 1569... |
Line 1570... |
output write;
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output write;
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output read;
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output read;
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output beginbursttransfer;
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output beginbursttransfer;
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output [3:0] burstcount;
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output [3:0] burstcount;
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input waitrequest;
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input waitrequest;
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input init_done;
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input clk, rst;
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input clk, rst;
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reg last_cyc_idle_or_eoc;
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// cnt1 - initiated read or writes
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// cnt2 - # of read or writes in pipeline
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reg [3:0] cnt1;
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reg [3:0] cnt1;
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reg next_state, state;
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localparam s0 = 1'b0;
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localparam s1 = 1'b1;
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wire eoc;
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always @ *
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begin
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case (state)
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s0: if (init_done & wbs_cyc_i) next_state <= s1;
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s1: if (cnt2==4'h1 & )
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default: next_state <= state;
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end
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end
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reg [3:0] cnt;
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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if (rst)
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if (rst)
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cnt <= 4'h0;
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state <= s0;
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else
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else
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if (beginbursttransfer & waitrequest)
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state <= next_state;
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cnt <= burst_size - 1;
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else if (beginbursttransfer & !waitrequest)
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assign eoc = state==s1 & !(read | write) & (& !waitrequest & cnt2=;
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cnt <= burst_size - 2;
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always @ (posedge clk or posedge rst)
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else if (wbs_ack_o)
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if (rst)
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cnt <= cnt - 1;
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cnt1 <= 4'h0;
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else
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if (read & !waitrequest & init_done)
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cnt1 <= burst_size - 1;
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else if (write & !waitrequest & init_done)
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cnt1 <= cnt1 + 4'h1;
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else if (next_state==idle)
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cnt1 <= 4'h0;
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always @ (posedge clk or posedge rst)
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if (rst)
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cnt2 <= 4'h0;
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else
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if (read & !waitrequest & init_done)
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cnt2 <= burst_size - 1;
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else if (write & !waitrequest & init_done & )
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cnt2 <= cnt1 + 4'h1;
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else if (next_state==idle)
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cnt2 <= 4'h0;
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reg wr_ack;
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reg wr_ack;
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always @ (posedge clk or posedge rst)
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always @ (posedge clk or posedge rst)
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if (rst)
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if (rst)
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wr_ack <= 1'b0;
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wr_ack <= 1'b0;
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Line 1596... |
Line 1633... |
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// to avalon
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// to avalon
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assign writedata = wbs_dat_i;
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assign writedata = wbs_dat_i;
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assign address = wbs_adr_i;
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assign address = wbs_adr_i;
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assign be = wbs_sel_i;
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assign be = wbs_sel_i;
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assign write = cnt==(burst_size-1) & wbs_cyc_i & wbs_we_i;
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assign write = cnt!=4'h0 & wbs_cyc_i & wbs_we_i;
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assign read = cnt==(burst_size-1) & wbs_cyc_i & !wbs_we_i;
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assign read = cnt!=4'h0 & wbs_cyc_i & !wbs_we_i;
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assign beginbursttransfer = cnt==4'h0 & wbs_cyc_i;
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assign beginbursttransfer = state==s0 & next_state==s1;
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assign burstcount = burst_size;
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assign burstcount = burst_size;
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// to wishbone
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// to wishbone
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assign wbs_dat_o = readdata;
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assign wbs_dat_o = readdata;
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assign wbs_ack_o = wr_ack | readdatavalid;
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assign wbs_ack_o = wr_ack | readdatavalid;
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