OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [wb.v] - Diff between revs 136 and 137

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 136 Rev 137
Line 1315... Line 1315...
wire done, mem_alert, mem_done;
wire done, mem_alert, mem_done;
 
 
// wbm side
// wbm side
reg [aw_m-1:0] wbm_radr;
reg [aw_m-1:0] wbm_radr;
reg [aw_m-1:0] wbm_wadr;
reg [aw_m-1:0] wbm_wadr;
wire [aw_slot-1:0] wbm_adr;
//wire [aw_slot-1:0] wbm_adr;
 
wire [aw_m-1:0] wbm_adr;
wire wbm_radr_cke, wbm_wadr_cke;
wire wbm_radr_cke, wbm_wadr_cke;
 
 
reg [2:0] phase;
reg [2:0] phase;
// phase = {we,stb,cyc}
// phase = {we,stb,cyc}
localparam wbm_wait     = 3'b000;
localparam wbm_wait     = 3'b000;
Line 1520... Line 1521...
endgenerate
endgenerate
 
 
assign mem_done = phase==wbm_rd_drain & (&cnt_ack) & wbm_ack_i;
assign mem_done = phase==wbm_rd_drain & (&cnt_ack) & wbm_ack_i;
 
 
assign wbm_adr_o = (phase[2]) ? {tag, wbs_adr_slot, cnt_rw} : {wbs_adr_tag, wbs_adr_slot, cnt_rw};
assign wbm_adr_o = (phase[2]) ? {tag, wbs_adr_slot, cnt_rw} : {wbs_adr_tag, wbs_adr_slot, cnt_rw};
assign wbm_adr   = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_rw};
assign wbm_adr   = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_ack};
assign wbm_sel_o = {dw_m/8{1'b1}};
assign wbm_sel_o = {dw_m/8{1'b1}};
assign wbm_cti_o = (&cnt_rw | !wbm_stb_o) ? 3'b111 : 3'b010;
assign wbm_cti_o = (&cnt_rw | !wbm_stb_o) ? 3'b111 : 3'b010;
assign wbm_bte_o = bte;
assign wbm_bte_o = bte;
assign {wbm_we_o, wbm_stb_o, wbm_cyc_o}  = phase;
assign {wbm_we_o, wbm_stb_o, wbm_cyc_o}  = phase;
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.