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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [wb.v] - Diff between revs 32 and 33

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Line 86... Line 86...
parameter wbs_data = 1'b1;
parameter wbs_data = 1'b1;
 
 
parameter wbm_adr0 = 2'b00;
parameter wbm_adr0 = 2'b00;
parameter wbm_adr1 = 2'b01;
parameter wbm_adr1 = 2'b01;
parameter wbm_data = 2'b10;
parameter wbm_data = 2'b10;
 
parameter wbm_data_wait = 2'b11;
 
 
reg [1:0] wbs_bte_reg;
reg [1:0] wbs_bte_reg;
reg wbs;
reg wbs;
wire wbs_eoc_alert, wbm_eoc_alert;
wire wbs_eoc_alert, wbm_eoc_alert;
reg wbs_eoc, wbm_eoc;
reg wbs_eoc, wbm_eoc;
Line 169... Line 170...
 
 
always @ (posedge wbm_clk or posedge wbm_rst)
always @ (posedge wbm_clk or posedge wbm_rst)
if (wbm_rst)
if (wbm_rst)
        wbm <= wbm_adr0;
        wbm <= wbm_adr0;
else
else
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
/*
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
        (wbm==wbm_adr1 & !wbm_we_o) |
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
        (wbm==wbm_adr1 & !wbm_we_o) |
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
 
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
 
*/
 
    case (wbm)
 
    wbm_adr0:
 
        if (!b_fifo_empty)
 
            wbm <= wbm_adr1;
 
    wbm_adr1:
 
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
 
            wbm <= wbm_data;
 
    wbm_data:
 
        if (wbm_ack_i & wbm_eoc)
 
            wbm <= wbm_adr0;
 
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
 
            wbm <= wbm_data_wait;
 
    wbm_data_wait:
 
        if (!b_fifo_empty)
 
            wbm <= wbm_data;
 
    endcase
 
 
assign b_d = {wbm_dat_i,4'b1111};
assign b_d = {wbm_dat_i,4'b1111};
assign b_wr = !wbm_we_o & wbm_ack_i;
assign b_wr = !wbm_we_o & wbm_ack_i;
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
 
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
                   1'b0;
                   1'b0;
assign b_rd = b_rd_adr | b_rd_data;
assign b_rd = b_rd_adr | b_rd_data;
 
 
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
Line 196... Line 216...
        .clear(wbm_eoc),
        .clear(wbm_eoc),
        .q(wbm_count),
        .q(wbm_count),
        .rst(wbm_rst),
        .rst(wbm_rst),
        .clk(wbm_clk));
        .clk(wbm_clk));
 
 
assign wbm_cyc_o = wbm==wbm_data;
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
assign wbm_stb_o = (wbm==wbm_data & wbm_we_o) ? !b_fifo_empty :
assign wbm_stb_o = (wbm==wbm_data);
                   (wbm==wbm_data) ? 1'b1 :
 
                   1'b0;
 
 
 
always @ (posedge wbm_clk or posedge wbm_rst)
always @ (posedge wbm_clk or posedge wbm_rst)
if (wbm_rst)
if (wbm_rst)
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
else begin
else begin
Line 246... Line 264...
 
 
    parameter adr_hi = 31;
    parameter adr_hi = 31;
    parameter adr_lo = 28;
    parameter adr_lo = 28;
    parameter adr_sel = 4'hf;
    parameter adr_sel = 4'hf;
    parameter addr_width = 5;
    parameter addr_width = 5;
 
/*
//E2_ifndef BOOT_ROM
//E2_ifndef BOOT_ROM
//E2_define BOOT_ROM "boot_rom.v"
//E2_define BOOT_ROM "boot_rom.v"
//E2_endif
//E2_endif
 
*/
    input [adr_hi:2]    wb_adr_i;
    input [adr_hi:2]    wb_adr_i;
    input               wb_stb_i;
    input               wb_stb_i;
    input               wb_cyc_i;
    input               wb_cyc_i;
    output [31:0]        wb_dat_o;
    output [31:0]        wb_dat_o;
    output              wb_ack_o;
    output              wb_ack_o;
Line 271... Line 289...
always @ (posedge wb_clk or posedge wb_rst)
always @ (posedge wb_clk or posedge wb_rst)
    if (wb_rst)
    if (wb_rst)
        wb_dat <= 32'h15000000;
        wb_dat <= 32'h15000000;
    else
    else
         case (wb_adr_i[addr_width-1:2])
         case (wb_adr_i[addr_width-1:2])
 
//E2_ifdef BOOT_ROM
//E2_include `BOOT_ROM
//E2_include `BOOT_ROM
 
//E2_endif
           /*
           /*
            // Zero r0 and jump to 0x00000100
            // Zero r0 and jump to 0x00000100
            0 : wb_dat <= 32'h18000000;
            0 : wb_dat <= 32'h18000000;
            1 : wb_dat <= 32'hA8200000;
            1 : wb_dat <= 32'hA8200000;
            2 : wb_dat <= 32'hA8C00100;
            2 : wb_dat <= 32'hA8C00100;
Line 329... Line 349...
input wbsb_clk, wbsb_rst;
input wbsb_clk, wbsb_rst;
 
 
wire wbsa_dat_tmp, wbsb_dat_tmp;
wire wbsa_dat_tmp, wbsb_dat_tmp;
 
 
vl_dpram_2r2w # (
vl_dpram_2r2w # (
    .data_width(data_width), addr_width(addr_width) )
    .data_width(data_width), .addr_width(addr_width) )
dpram0(
dpram0(
    .d_a(wbsa_dat_i),
    .d_a(wbsa_dat_i),
    .q_a(wbsa_dat_tmp),
    .q_a(wbsa_dat_tmp),
    .adr_a(wbsa_adr_i),
    .adr_a(wbsa_adr_i),
    .we_a(wbsa_we_i),
    .we_a(wbsa_we_i),
Line 342... Line 362...
    .q_b(wbsb_dat_tmp),
    .q_b(wbsb_dat_tmp),
    .adr_b(wbsb_adr_i),
    .adr_b(wbsb_adr_i),
    .we_b(wbsb_we_i),
    .we_b(wbsb_we_i),
    .clk_b(wbsb_clk) );
    .clk_b(wbsb_clk) );
 
 
if (dat_o_mask_a==1) generate
generate if (dat_o_mask_a==1)
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
endgenerate
endgenerate
if (dat_o_mask_a==0) generate
generate if (dat_o_mask_a==0)
    assign wbsa_dat_o = wbsa_dat_tmp;
    assign wbsa_dat_o = wbsa_dat_tmp;
endgenerate
endgenerate
 
 
if (dat_o_mask_b==1) generate
generate if (dat_o_mask_b==1)
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
endgenerate
endgenerate
if (dat_o_mask_b==0) generate
generate if (dat_o_mask_b==0)
    assign wbsb_dat_o = wbsb_dat_tmp;
    assign wbsb_dat_o = wbsb_dat_tmp;
endgenerate
endgenerate
 
 
vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));

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