//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Versatile library, wishbone stuff ////
|
//// Versatile library, wishbone stuff ////
|
//// ////
|
//// ////
|
//// Description ////
|
//// Description ////
|
//// Wishbone compliant modules ////
|
//// Wishbone compliant modules ////
|
//// ////
|
//// ////
|
//// ////
|
//// ////
|
//// To Do: ////
|
//// To Do: ////
|
//// - ////
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//// - ////
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//// ////
|
//// ////
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//// Author(s): ////
|
//// Author(s): ////
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//// - Michael Unneback, unneback@opencores.org ////
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//// - Michael Unneback, unneback@opencores.org ////
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//// ORSoC AB ////
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//// ORSoC AB ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
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//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
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//// later version. ////
|
//// ////
|
//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
|
//// details. ////
|
//// ////
|
//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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// async wb3 - wb3 bridge
|
// async wb3 - wb3 bridge
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`timescale 1ns/1ns
|
`timescale 1ns/1ns
|
module vl_wb3wb3_bridge (
|
module vl_wb3wb3_bridge (
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// wishbone slave side
|
// wishbone slave side
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
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// wishbone master side
|
// wishbone master side
|
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
|
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
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|
|
input [31:0] wbs_dat_i;
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input [31:0] wbs_dat_i;
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input [31:2] wbs_adr_i;
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input [31:2] wbs_adr_i;
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input [3:0] wbs_sel_i;
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input [3:0] wbs_sel_i;
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input [1:0] wbs_bte_i;
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input [1:0] wbs_bte_i;
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input [2:0] wbs_cti_i;
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input [2:0] wbs_cti_i;
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input wbs_we_i, wbs_cyc_i, wbs_stb_i;
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input wbs_we_i, wbs_cyc_i, wbs_stb_i;
|
output [31:0] wbs_dat_o;
|
output [31:0] wbs_dat_o;
|
output wbs_ack_o;
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output wbs_ack_o;
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input wbs_clk, wbs_rst;
|
input wbs_clk, wbs_rst;
|
|
|
output [31:0] wbm_dat_o;
|
output [31:0] wbm_dat_o;
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output reg [31:2] wbm_adr_o;
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output reg [31:2] wbm_adr_o;
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output [3:0] wbm_sel_o;
|
output [3:0] wbm_sel_o;
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output reg [1:0] wbm_bte_o;
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output reg [1:0] wbm_bte_o;
|
output reg [2:0] wbm_cti_o;
|
output reg [2:0] wbm_cti_o;
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output reg wbm_we_o;
|
output reg wbm_we_o;
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output wbm_cyc_o;
|
output wbm_cyc_o;
|
output wbm_stb_o;
|
output wbm_stb_o;
|
input [31:0] wbm_dat_i;
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input [31:0] wbm_dat_i;
|
input wbm_ack_i;
|
input wbm_ack_i;
|
input wbm_clk, wbm_rst;
|
input wbm_clk, wbm_rst;
|
|
|
parameter addr_width = 4;
|
parameter addr_width = 4;
|
|
|
// bte
|
// bte
|
parameter linear = 2'b00;
|
parameter linear = 2'b00;
|
parameter wrap4 = 2'b01;
|
parameter wrap4 = 2'b01;
|
parameter wrap8 = 2'b10;
|
parameter wrap8 = 2'b10;
|
parameter wrap16 = 2'b11;
|
parameter wrap16 = 2'b11;
|
// cti
|
// cti
|
parameter classic = 3'b000;
|
parameter classic = 3'b000;
|
parameter incburst = 3'b010;
|
parameter incburst = 3'b010;
|
parameter endofburst = 3'b111;
|
parameter endofburst = 3'b111;
|
|
|
parameter wbs_adr = 1'b0;
|
parameter wbs_adr = 1'b0;
|
parameter wbs_data = 1'b1;
|
parameter wbs_data = 1'b1;
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|
|
parameter wbm_adr0 = 2'b00;
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parameter wbm_adr0 = 2'b00;
|
parameter wbm_adr1 = 2'b01;
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parameter wbm_adr1 = 2'b01;
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parameter wbm_data = 2'b10;
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parameter wbm_data = 2'b10;
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|
parameter wbm_data_wait = 2'b11;
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|
|
reg [1:0] wbs_bte_reg;
|
reg [1:0] wbs_bte_reg;
|
reg wbs;
|
reg wbs;
|
wire wbs_eoc_alert, wbm_eoc_alert;
|
wire wbs_eoc_alert, wbm_eoc_alert;
|
reg wbs_eoc, wbm_eoc;
|
reg wbs_eoc, wbm_eoc;
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reg [1:0] wbm;
|
reg [1:0] wbm;
|
|
|
wire [1:16] wbs_count, wbm_count;
|
wire [1:16] wbs_count, wbm_count;
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|
|
wire [35:0] a_d, a_q, b_d, b_q;
|
wire [35:0] a_d, a_q, b_d, b_q;
|
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
|
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
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reg a_rd_reg;
|
reg a_rd_reg;
|
wire b_rd_adr, b_rd_data;
|
wire b_rd_adr, b_rd_data;
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wire b_rd_data_reg;
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wire b_rd_data_reg;
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wire [35:0] temp;
|
wire [35:0] temp;
|
|
|
`define WE 5
|
`define WE 5
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`define BTE 4:3
|
`define BTE 4:3
|
`define CTI 2:0
|
`define CTI 2:0
|
|
|
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
|
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
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always @ (posedge wbs_clk or posedge wbs_rst)
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
if (wbs_rst)
|
if (wbs_rst)
|
wbs_eoc <= 1'b0;
|
wbs_eoc <= 1'b0;
|
else
|
else
|
if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
|
if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
|
wbs_eoc <= wbs_bte_i==linear;
|
wbs_eoc <= wbs_bte_i==linear;
|
else if (wbs_eoc_alert & (a_rd | a_wr))
|
else if (wbs_eoc_alert & (a_rd | a_wr))
|
wbs_eoc <= 1'b1;
|
wbs_eoc <= 1'b1;
|
|
|
vl_cnt_shreg_ce_clear # ( .length(16))
|
vl_cnt_shreg_ce_clear # ( .length(16))
|
cnt0 (
|
cnt0 (
|
.cke(wbs_ack_o),
|
.cke(wbs_ack_o),
|
.clear(wbs_eoc),
|
.clear(wbs_eoc),
|
.q(wbs_count),
|
.q(wbs_count),
|
.rst(wbs_rst),
|
.rst(wbs_rst),
|
.clk(wbs_clk));
|
.clk(wbs_clk));
|
|
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
if (wbs_rst)
|
if (wbs_rst)
|
wbs <= wbs_adr;
|
wbs <= wbs_adr;
|
else
|
else
|
if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
|
if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
|
wbs <= wbs_data;
|
wbs <= wbs_data;
|
else if (wbs_eoc & wbs_ack_o)
|
else if (wbs_eoc & wbs_ack_o)
|
wbs <= wbs_adr;
|
wbs <= wbs_adr;
|
|
|
// wbs FIFO
|
// wbs FIFO
|
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
|
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
|
assign a_wr = (wbs==wbs_adr) ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
|
assign a_wr = (wbs==wbs_adr) ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
|
(wbs==wbs_data) ? wbs_we_i & wbs_stb_i & !a_fifo_full :
|
(wbs==wbs_data) ? wbs_we_i & wbs_stb_i & !a_fifo_full :
|
1'b0;
|
1'b0;
|
assign a_rd = !a_fifo_empty;
|
assign a_rd = !a_fifo_empty;
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
if (wbs_rst)
|
if (wbs_rst)
|
a_rd_reg <= 1'b0;
|
a_rd_reg <= 1'b0;
|
else
|
else
|
a_rd_reg <= a_rd;
|
a_rd_reg <= a_rd;
|
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
|
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
|
|
|
assign wbs_dat_o = a_q[35:4];
|
assign wbs_dat_o = a_q[35:4];
|
|
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
if (wbs_rst)
|
if (wbs_rst)
|
wbs_bte_reg <= 2'b00;
|
wbs_bte_reg <= 2'b00;
|
else
|
else
|
wbs_bte_reg <= wbs_bte_i;
|
wbs_bte_reg <= wbs_bte_i;
|
|
|
// wbm FIFO
|
// wbm FIFO
|
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
|
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
if (wbm_rst)
|
if (wbm_rst)
|
wbm_eoc <= 1'b0;
|
wbm_eoc <= 1'b0;
|
else
|
else
|
if (wbm==wbm_adr0 & !b_fifo_empty)
|
if (wbm==wbm_adr0 & !b_fifo_empty)
|
wbm_eoc <= b_q[`BTE] == linear;
|
wbm_eoc <= b_q[`BTE] == linear;
|
else if (wbm_eoc_alert & wbm_ack_i)
|
else if (wbm_eoc_alert & wbm_ack_i)
|
wbm_eoc <= 1'b1;
|
wbm_eoc <= 1'b1;
|
|
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
if (wbm_rst)
|
if (wbm_rst)
|
wbm <= wbm_adr0;
|
wbm <= wbm_adr0;
|
else
|
else
|
if ((wbm==wbm_adr0 & !b_fifo_empty) |
|
/*
|
(wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
|
if ((wbm==wbm_adr0 & !b_fifo_empty) |
|
(wbm==wbm_adr1 & !wbm_we_o) |
|
(wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
|
(wbm==wbm_data & wbm_ack_i & wbm_eoc))
|
(wbm==wbm_adr1 & !wbm_we_o) |
|
wbm <= {wbm[0],!(wbm[1] ^ wbm[0])}; // count sequence 00,01,10
|
(wbm==wbm_data & wbm_ack_i & wbm_eoc))
|
|
wbm <= {wbm[0],!(wbm[1] ^ wbm[0])}; // count sequence 00,01,10
|
|
*/
|
|
case (wbm)
|
|
wbm_adr0:
|
|
if (!b_fifo_empty)
|
|
wbm <= wbm_adr1;
|
|
wbm_adr1:
|
|
if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
|
|
wbm <= wbm_data;
|
|
wbm_data:
|
|
if (wbm_ack_i & wbm_eoc)
|
|
wbm <= wbm_adr0;
|
|
else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
|
|
wbm <= wbm_data_wait;
|
|
wbm_data_wait:
|
|
if (!b_fifo_empty)
|
|
wbm <= wbm_data;
|
|
endcase
|
|
|
assign b_d = {wbm_dat_i,4'b1111};
|
assign b_d = {wbm_dat_i,4'b1111};
|
assign b_wr = !wbm_we_o & wbm_ack_i;
|
assign b_wr = !wbm_we_o & wbm_ack_i;
|
assign b_rd_adr = (wbm==wbm_adr0 & !b_fifo_empty);
|
assign b_rd_adr = (wbm==wbm_adr0 & !b_fifo_empty);
|
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
|
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
|
(wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
|
(wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
|
|
(wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
|
1'b0;
|
1'b0;
|
assign b_rd = b_rd_adr | b_rd_data;
|
assign b_rd = b_rd_adr | b_rd_data;
|
|
|
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
|
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
|
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
|
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
|
|
|
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
|
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
|
|
|
vl_cnt_shreg_ce_clear # ( .length(16))
|
vl_cnt_shreg_ce_clear # ( .length(16))
|
cnt1 (
|
cnt1 (
|
.cke(wbm_ack_i),
|
.cke(wbm_ack_i),
|
.clear(wbm_eoc),
|
.clear(wbm_eoc),
|
.q(wbm_count),
|
.q(wbm_count),
|
.rst(wbm_rst),
|
.rst(wbm_rst),
|
.clk(wbm_clk));
|
.clk(wbm_clk));
|
|
|
assign wbm_cyc_o = wbm==wbm_data;
|
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
|
assign wbm_stb_o = (wbm==wbm_data & wbm_we_o) ? !b_fifo_empty :
|
assign wbm_stb_o = (wbm==wbm_data);
|
(wbm==wbm_data) ? 1'b1 :
|
|
1'b0;
|
|
|
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
if (wbm_rst)
|
if (wbm_rst)
|
{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
|
{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
|
else begin
|
else begin
|
if (wbm==wbm_adr0 & !b_fifo_empty)
|
if (wbm==wbm_adr0 & !b_fifo_empty)
|
{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
|
{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
|
else if (wbm_eoc_alert & wbm_ack_i)
|
else if (wbm_eoc_alert & wbm_ack_i)
|
wbm_cti_o <= endofburst;
|
wbm_cti_o <= endofburst;
|
end
|
end
|
|
|
//async_fifo_dw_simplex_top
|
//async_fifo_dw_simplex_top
|
vl_fifo_2r2w_async_simplex
|
vl_fifo_2r2w_async_simplex
|
# ( .data_width(36), .addr_width(addr_width))
|
# ( .data_width(36), .addr_width(addr_width))
|
fifo (
|
fifo (
|
// a side
|
// a side
|
.a_d(a_d),
|
.a_d(a_d),
|
.a_wr(a_wr),
|
.a_wr(a_wr),
|
.a_fifo_full(a_fifo_full),
|
.a_fifo_full(a_fifo_full),
|
.a_q(a_q),
|
.a_q(a_q),
|
.a_rd(a_rd),
|
.a_rd(a_rd),
|
.a_fifo_empty(a_fifo_empty),
|
.a_fifo_empty(a_fifo_empty),
|
.a_clk(wbs_clk),
|
.a_clk(wbs_clk),
|
.a_rst(wbs_rst),
|
.a_rst(wbs_rst),
|
// b side
|
// b side
|
.b_d(b_d),
|
.b_d(b_d),
|
.b_wr(b_wr),
|
.b_wr(b_wr),
|
.b_fifo_full(b_fifo_full),
|
.b_fifo_full(b_fifo_full),
|
.b_q(b_q),
|
.b_q(b_q),
|
.b_rd(b_rd),
|
.b_rd(b_rd),
|
.b_fifo_empty(b_fifo_empty),
|
.b_fifo_empty(b_fifo_empty),
|
.b_clk(wbm_clk),
|
.b_clk(wbm_clk),
|
.b_rst(wbm_rst)
|
.b_rst(wbm_rst)
|
);
|
);
|
|
|
endmodule
|
endmodule
|
|
|
// WB ROM
|
// WB ROM
|
module vl_wb_boot_rom (
|
module vl_wb_boot_rom (
|
wb_adr_i, wb_stb_i, wb_cyc_i,
|
wb_adr_i, wb_stb_i, wb_cyc_i,
|
wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
|
wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
|
|
|
parameter adr_hi = 31;
|
parameter adr_hi = 31;
|
parameter adr_lo = 28;
|
parameter adr_lo = 28;
|
parameter adr_sel = 4'hf;
|
parameter adr_sel = 4'hf;
|
parameter addr_width = 5;
|
parameter addr_width = 5;
|
|
/*
|
//E2_ifndef BOOT_ROM
|
//E2_ifndef BOOT_ROM
|
//E2_define BOOT_ROM "boot_rom.v"
|
//E2_define BOOT_ROM "boot_rom.v"
|
//E2_endif
|
//E2_endif
|
|
*/
|
input [adr_hi:2] wb_adr_i;
|
input [adr_hi:2] wb_adr_i;
|
input wb_stb_i;
|
input wb_stb_i;
|
input wb_cyc_i;
|
input wb_cyc_i;
|
output [31:0] wb_dat_o;
|
output [31:0] wb_dat_o;
|
output wb_ack_o;
|
output wb_ack_o;
|
output hit_o;
|
output hit_o;
|
input wb_clk;
|
input wb_clk;
|
input wb_rst;
|
input wb_rst;
|
|
|
wire hit;
|
wire hit;
|
reg [31:0] wb_dat;
|
reg [31:0] wb_dat;
|
reg wb_ack;
|
reg wb_ack;
|
|
|
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
|
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
|
|
|
always @ (posedge wb_clk or posedge wb_rst)
|
always @ (posedge wb_clk or posedge wb_rst)
|
if (wb_rst)
|
if (wb_rst)
|
wb_dat <= 32'h15000000;
|
wb_dat <= 32'h15000000;
|
else
|
else
|
case (wb_adr_i[addr_width-1:2])
|
case (wb_adr_i[addr_width-1:2])
|
|
//E2_ifdef BOOT_ROM
|
//E2_include `BOOT_ROM
|
//E2_include `BOOT_ROM
|
|
//E2_endif
|
/*
|
/*
|
// Zero r0 and jump to 0x00000100
|
// Zero r0 and jump to 0x00000100
|
0 : wb_dat <= 32'h18000000;
|
0 : wb_dat <= 32'h18000000;
|
1 : wb_dat <= 32'hA8200000;
|
1 : wb_dat <= 32'hA8200000;
|
2 : wb_dat <= 32'hA8C00100;
|
2 : wb_dat <= 32'hA8C00100;
|
3 : wb_dat <= 32'h44003000;
|
3 : wb_dat <= 32'h44003000;
|
4 : wb_dat <= 32'h15000000;
|
4 : wb_dat <= 32'h15000000;
|
*/
|
*/
|
default:
|
default:
|
wb_dat <= 32'h00000000;
|
wb_dat <= 32'h00000000;
|
|
|
endcase // case (wb_adr_i)
|
endcase // case (wb_adr_i)
|
|
|
|
|
always @ (posedge wb_clk or posedge wb_rst)
|
always @ (posedge wb_clk or posedge wb_rst)
|
if (wb_rst)
|
if (wb_rst)
|
wb_ack <= 1'b0;
|
wb_ack <= 1'b0;
|
else
|
else
|
wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
|
wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
|
|
|
assign hit_o = hit;
|
assign hit_o = hit;
|
assign wb_dat_o = wb_dat & {32{wb_ack}};
|
assign wb_dat_o = wb_dat & {32{wb_ack}};
|
assign wb_ack_o = wb_ack;
|
assign wb_ack_o = wb_ack;
|
|
|
endmodule
|
endmodule
|
|
|
module vl_wb_dpram (
|
module vl_wb_dpram (
|
// wishbone slave side a
|
// wishbone slave side a
|
wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
|
wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
|
wbsa_clk, wbsa_rst,
|
wbsa_clk, wbsa_rst,
|
// wishbone slave side a
|
// wishbone slave side a
|
wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
|
wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
|
wbsb_clk, wbsb_rst);
|
wbsb_clk, wbsb_rst);
|
|
|
parameter data_width = 32;
|
parameter data_width = 32;
|
parameter addr_width = 8;
|
parameter addr_width = 8;
|
|
|
parameter dat_o_mask_a = 1;
|
parameter dat_o_mask_a = 1;
|
parameter dat_o_mask_b = 1;
|
parameter dat_o_mask_b = 1;
|
|
|
input [31:0] wbsa_dat_i;
|
input [31:0] wbsa_dat_i;
|
input [addr_width-1:2] wbsa_adr_i;
|
input [addr_width-1:2] wbsa_adr_i;
|
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
|
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
|
output [31:0] wbsa_dat_o;
|
output [31:0] wbsa_dat_o;
|
output wbsa_ack_o;
|
output wbsa_ack_o;
|
input wbsa_clk, wbsa_rst;
|
input wbsa_clk, wbsa_rst;
|
|
|
input [31:0] wbsb_dat_i;
|
input [31:0] wbsb_dat_i;
|
input [addr_width-1:2] wbsb_adr_i;
|
input [addr_width-1:2] wbsb_adr_i;
|
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
|
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
|
output [31:0] wbsb_dat_o;
|
output [31:0] wbsb_dat_o;
|
output wbsb_ack_o;
|
output wbsb_ack_o;
|
input wbsb_clk, wbsb_rst;
|
input wbsb_clk, wbsb_rst;
|
|
|
wire wbsa_dat_tmp, wbsb_dat_tmp;
|
wire wbsa_dat_tmp, wbsb_dat_tmp;
|
|
|
vl_dpram_2r2w # (
|
vl_dpram_2r2w # (
|
.data_width(data_width), addr_width(addr_width) )
|
.data_width(data_width), .addr_width(addr_width) )
|
dpram0(
|
dpram0(
|
.d_a(wbsa_dat_i),
|
.d_a(wbsa_dat_i),
|
.q_a(wbsa_dat_tmp),
|
.q_a(wbsa_dat_tmp),
|
.adr_a(wbsa_adr_i),
|
.adr_a(wbsa_adr_i),
|
.we_a(wbsa_we_i),
|
.we_a(wbsa_we_i),
|
.clk_a(wbsa_clk),
|
.clk_a(wbsa_clk),
|
.d_b(wbsb_dat_i),
|
.d_b(wbsb_dat_i),
|
.q_b(wbsb_dat_tmp),
|
.q_b(wbsb_dat_tmp),
|
.adr_b(wbsb_adr_i),
|
.adr_b(wbsb_adr_i),
|
.we_b(wbsb_we_i),
|
.we_b(wbsb_we_i),
|
.clk_b(wbsb_clk) );
|
.clk_b(wbsb_clk) );
|
|
|
if (dat_o_mask_a==1) generate
|
generate if (dat_o_mask_a==1)
|
assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
|
assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
|
endgenerate
|
endgenerate
|
if (dat_o_mask_a==0) generate
|
generate if (dat_o_mask_a==0)
|
assign wbsa_dat_o = wbsa_dat_tmp;
|
assign wbsa_dat_o = wbsa_dat_tmp;
|
endgenerate
|
endgenerate
|
|
|
if (dat_o_mask_b==1) generate
|
generate if (dat_o_mask_b==1)
|
assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
|
assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
|
endgenerate
|
endgenerate
|
if (dat_o_mask_b==0) generate
|
generate if (dat_o_mask_b==0)
|
assign wbsb_dat_o = wbsb_dat_tmp;
|
assign wbsb_dat_o = wbsb_dat_tmp;
|
endgenerate
|
endgenerate
|
|
|
vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
|
vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
|
vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
|
vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
|
|
|
endmodule
|
endmodule
|
|
|