| Line 218... |
Line 218... |
`undef MODULE
|
`undef MODULE
|
|
|
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
|
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
|
|
|
`define MODULE cnt_shreg_ce_clear
|
`define MODULE cnt_shreg_ce_clear
|
vl_cnt_shreg_ce_clear # ( .length(16))
|
`BASE`MODULE # ( .length(16))
|
`undef MODULE
|
`undef MODULE
|
cnt1 (
|
cnt1 (
|
.cke(wbm_ack_i),
|
.cke(wbm_ack_i),
|
.clear(wbm_eoc),
|
.clear(wbm_eoc),
|
.q(wbm_count),
|
.q(wbm_count),
|
| Line 274... |
Line 274... |
`undef CTI
|
`undef CTI
|
`endif
|
`endif
|
|
|
`ifdef WB3_ARBITER_TYPE1
|
`ifdef WB3_ARBITER_TYPE1
|
`define MODULE wb3_arbiter_type1
|
`define MODULE wb3_arbiter_type1
|
module vl_wb3_arbiter_type1 (
|
module `BASE`MODULE (
|
`undef MODULE
|
`undef MODULE
|
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
|
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
|
wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
|
wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
|
wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
|
wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
|
| Line 356... |
Line 356... |
end
|
end
|
endgenerate
|
endgenerate
|
|
|
generate
|
generate
|
for (i=0;i<nr_of_ports;i=i+1) begin
|
for (i=0;i<nr_of_ports;i=i+1) begin
|
vl_spr sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
|
`define MODULE spr
|
|
`BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
|
|
`undef MODULE
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
assign sel = select | state;
|
assign sel = select | state;
|
|
|
