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Line 465... |
assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
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assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
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endmodule
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endmodule
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`endif
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`endif
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`ifdef WB_B4_ROM
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// WB ROM
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`define MODULE wb_b4_rom
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module `BASE`MODULE (
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`undef MODULE
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wb_adr_i, wb_stb_i, wb_cyc_i,
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wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
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parameter dat_width = 32;
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parameter dat_default = 32'h15000000;
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parameter adr_width = 32;
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/*
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//E2_ifndef ROM
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//E2_define ROM "rom.v"
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//E2_endif
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*/
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input [adr_width-1:2] wb_adr_i;
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input wb_stb_i;
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input wb_cyc_i;
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output [dat_width-1:0] wb_dat_o;
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reg [dat_width-1:0] wb_dat_o;
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output wb_ack_o;
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reg wb_ack_o;
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output stall_o;
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input wb_clk;
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input wb_rst;
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always @ (posedge wb_clk or posedge wb_rst)
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if (wb_rst)
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wb_dat_o <= {dat_width{1'b0}};
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else
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case (wb_adr_i[adr_width-1:2])
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//E2_ifdef ROM
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//E2_include `ROM
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//E2_endif
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default:
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wb_dat_o <= dat_default;
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endcase // case (wb_adr_i)
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always @ (posedge wb_clk or posedge wb_rst)
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if (wb_rst)
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wb_ack_o <= 1'b0;
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else
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wb_ack_o <= wb_stb_i & wb_cyc_i;
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assign stall_o = 1'b0;
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endmodule
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`endif
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`ifdef WB_BOOT_ROM
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`ifdef WB_BOOT_ROM
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// WB ROM
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// WB ROM
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`define MODULE wb_boot_rom
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`define MODULE wb_boot_rom
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module `BASE`MODULE (
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module `BASE`MODULE (
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`undef MODULE
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`undef MODULE
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