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// WB RAM with byte enable
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// WB RAM with byte enable
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`define MODULE wb_b4_ram_be
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`define MODULE wb_b4_ram_be
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module `BASE`MODULE (
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module `BASE`MODULE (
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`undef MODULE
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`undef MODULE
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wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
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wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
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wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
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wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
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parameter dat_width = 32;
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parameter dat_width = 32;
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parameter adr_width = 8;
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parameter adr_width = 8;
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input [dat_width-1:0] wb_dat_i;
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input [dat_width-1:0] wb_dat_i;
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input [adr_width-1:0] wb_adr_i;
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input [adr_width-1:0] wb_adr_i;
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input [dat_width/8-1:0] wb_sel_i;
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input [dat_width/8-1:0] wb_sel_i;
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input wb_we_i, wb_stb_i, wb_cyc_i;
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input wb_we_i, wb_stb_i, wb_cyc_i;
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output [dat_width-1:0] wb_dat_o;
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output [dat_width-1:0] wb_dat_o;
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reg [dat_width-1:0] wb_dat_o;
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reg [dat_width-1:0] wb_dat_o;
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output stall_o;
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output wb_stall_o;
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output wb_ack_o;
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output wb_ack_o;
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reg wb_ack_o;
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reg wb_ack_o;
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reg wb_ack_o;
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input wb_clk, wb_rst;
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input wb_clk, wb_rst;
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generate
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generate
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if (dat_width==32) begin
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if (dat_width==32) begin
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reg [7:0] ram3 [1<<(adr_width-2)-1:0];
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reg [7:0] ram3 [1<<(adr_width-2)-1:0];
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wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
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wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
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end
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end
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end
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end
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endgenerate
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endgenerate
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always @ (posedge wb_clk or posedge wb_rst)
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if (rst)
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wb_ack_o <= 1'b0;
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else
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wb_ack_o <= wb_stb_i & wb_cyc_i
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assign wb_stall_o = 1'b0;
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endmodule
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endmodule
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`endif
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`endif
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`ifdef WB_B4_ROM
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`ifdef WB_B4_ROM
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// WB ROM
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// WB ROM
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