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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [wb.v] - Diff between revs 52 and 53

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Rev 52 Rev 53
Line 485... Line 485... 
output [dat_width-1:0] wb_dat_o;
 
output [dat_width-1:0] wb_dat_o;
 
reg [dat_width-1:0] wb_dat_o;
 
reg [dat_width-1:0] wb_dat_o;
 
output wb_stall_o;
 
output wb_stall_o;
 
output wb_ack_o;
 
output wb_ack_o;
 
reg wb_ack_o;
 
reg wb_ack_o;
 
reg wb_ack_o;
 
 
 
input wb_clk, wb_rst;
 
input wb_clk, wb_rst;
 
 
 
 
 
generate
 
generate
 
if (dat_width==32) begin
 
if (dat_width==32) begin
 
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
 
reg [7:0] ram3 [1<<(adr_width-2)-1:0];

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