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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [wb.v] - Diff between revs 54 and 55

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Rev 54 Rev 55
Line 505... Line 505...
    end
    end
end
end
endgenerate
endgenerate
 
 
always @ (posedge wb_clk or posedge wb_rst)
always @ (posedge wb_clk or posedge wb_rst)
if (rst)
if (wb_rst)
    wb_ack_o <= 1'b0;
    wb_ack_o <= 1'b0;
else
else
    wb_ack_o <= wb_stb_i & wb_cyc_i;
    wb_ack_o <= wb_stb_i & wb_cyc_i;
 
 
assign wb_stall_o = 1'b0;
assign wb_stall_o = 1'b0;

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