//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
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//// ////
|
//// Versatile library, wishbone stuff ////
|
//// Versatile library, wishbone stuff ////
|
//// ////
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//// ////
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//// Description ////
|
//// Description ////
|
//// Wishbone compliant modules ////
|
//// Wishbone compliant modules ////
|
//// ////
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//// ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - ////
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//// - ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Michael Unneback, unneback@opencores.org ////
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//// - Michael Unneback, unneback@opencores.org ////
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//// ORSoC AB ////
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//// ORSoC AB ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// details. ////
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//// details. ////
|
//// ////
|
//// ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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`ifdef WB3WB3_BRIDGE
|
`ifdef WB3WB3_BRIDGE
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// async wb3 - wb3 bridge
|
// async wb3 - wb3 bridge
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`timescale 1ns/1ns
|
`timescale 1ns/1ns
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`define MODULE wb3wb3_bridge
|
`define MODULE wb3wb3_bridge
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module `BASE`MODULE (
|
module `BASE`MODULE (
|
`undef MODULE
|
`undef MODULE
|
// wishbone slave side
|
// wishbone slave side
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
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// wishbone master side
|
// wishbone master side
|
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
|
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
|
|
|
input [31:0] wbs_dat_i;
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input [31:0] wbs_dat_i;
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input [31:2] wbs_adr_i;
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input [31:2] wbs_adr_i;
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input [3:0] wbs_sel_i;
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input [3:0] wbs_sel_i;
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input [1:0] wbs_bte_i;
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input [1:0] wbs_bte_i;
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input [2:0] wbs_cti_i;
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input [2:0] wbs_cti_i;
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input wbs_we_i, wbs_cyc_i, wbs_stb_i;
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input wbs_we_i, wbs_cyc_i, wbs_stb_i;
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output [31:0] wbs_dat_o;
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output [31:0] wbs_dat_o;
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output wbs_ack_o;
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output wbs_ack_o;
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input wbs_clk, wbs_rst;
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input wbs_clk, wbs_rst;
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|
|
output [31:0] wbm_dat_o;
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output [31:0] wbm_dat_o;
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output reg [31:2] wbm_adr_o;
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output reg [31:2] wbm_adr_o;
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output [3:0] wbm_sel_o;
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output [3:0] wbm_sel_o;
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output reg [1:0] wbm_bte_o;
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output reg [1:0] wbm_bte_o;
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output reg [2:0] wbm_cti_o;
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output reg [2:0] wbm_cti_o;
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output reg wbm_we_o;
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output reg wbm_we_o;
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output wbm_cyc_o;
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output wbm_cyc_o;
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output wbm_stb_o;
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output wbm_stb_o;
|
input [31:0] wbm_dat_i;
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input [31:0] wbm_dat_i;
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input wbm_ack_i;
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input wbm_ack_i;
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input wbm_clk, wbm_rst;
|
input wbm_clk, wbm_rst;
|
|
|
parameter addr_width = 4;
|
parameter addr_width = 4;
|
|
|
// bte
|
// bte
|
parameter linear = 2'b00;
|
parameter linear = 2'b00;
|
parameter wrap4 = 2'b01;
|
parameter wrap4 = 2'b01;
|
parameter wrap8 = 2'b10;
|
parameter wrap8 = 2'b10;
|
parameter wrap16 = 2'b11;
|
parameter wrap16 = 2'b11;
|
// cti
|
// cti
|
parameter classic = 3'b000;
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parameter classic = 3'b000;
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parameter incburst = 3'b010;
|
parameter incburst = 3'b010;
|
parameter endofburst = 3'b111;
|
parameter endofburst = 3'b111;
|
|
|
parameter wbs_adr = 1'b0;
|
parameter wbs_adr = 1'b0;
|
parameter wbs_data = 1'b1;
|
parameter wbs_data = 1'b1;
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|
|
parameter wbm_adr0 = 2'b00;
|
parameter wbm_adr0 = 2'b00;
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parameter wbm_adr1 = 2'b01;
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parameter wbm_adr1 = 2'b01;
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parameter wbm_data = 2'b10;
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parameter wbm_data = 2'b10;
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parameter wbm_data_wait = 2'b11;
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parameter wbm_data_wait = 2'b11;
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|
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reg [1:0] wbs_bte_reg;
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reg [1:0] wbs_bte_reg;
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reg wbs;
|
reg wbs;
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wire wbs_eoc_alert, wbm_eoc_alert;
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wire wbs_eoc_alert, wbm_eoc_alert;
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reg wbs_eoc, wbm_eoc;
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reg wbs_eoc, wbm_eoc;
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reg [1:0] wbm;
|
reg [1:0] wbm;
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|
|
wire [1:16] wbs_count, wbm_count;
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wire [1:16] wbs_count, wbm_count;
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|
|
wire [35:0] a_d, a_q, b_d, b_q;
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wire [35:0] a_d, a_q, b_d, b_q;
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wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
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wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
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reg a_rd_reg;
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reg a_rd_reg;
|
wire b_rd_adr, b_rd_data;
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wire b_rd_adr, b_rd_data;
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wire b_rd_data_reg;
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wire b_rd_data_reg;
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wire [35:0] temp;
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wire [35:0] temp;
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|
|
`define WE 5
|
`define WE 5
|
`define BTE 4:3
|
`define BTE 4:3
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`define CTI 2:0
|
`define CTI 2:0
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|
|
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
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assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
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always @ (posedge wbs_clk or posedge wbs_rst)
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
if (wbs_rst)
|
if (wbs_rst)
|
wbs_eoc <= 1'b0;
|
wbs_eoc <= 1'b0;
|
else
|
else
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if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
|
if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
|
wbs_eoc <= wbs_bte_i==linear;
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wbs_eoc <= wbs_bte_i==linear;
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else if (wbs_eoc_alert & (a_rd | a_wr))
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else if (wbs_eoc_alert & (a_rd | a_wr))
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wbs_eoc <= 1'b1;
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wbs_eoc <= 1'b1;
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|
|
`define MODULE cnt_shreg_ce_clear
|
`define MODULE cnt_shreg_ce_clear
|
`BASE`MODULE # ( .length(16))
|
`BASE`MODULE # ( .length(16))
|
`undef MODULE
|
`undef MODULE
|
cnt0 (
|
cnt0 (
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.cke(wbs_ack_o),
|
.cke(wbs_ack_o),
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.clear(wbs_eoc),
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.clear(wbs_eoc),
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.q(wbs_count),
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.q(wbs_count),
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.rst(wbs_rst),
|
.rst(wbs_rst),
|
.clk(wbs_clk));
|
.clk(wbs_clk));
|
|
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
if (wbs_rst)
|
if (wbs_rst)
|
wbs <= wbs_adr;
|
wbs <= wbs_adr;
|
else
|
else
|
if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
|
if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
|
wbs <= wbs_data;
|
wbs <= wbs_data;
|
else if (wbs_eoc & wbs_ack_o)
|
else if (wbs_eoc & wbs_ack_o)
|
wbs <= wbs_adr;
|
wbs <= wbs_adr;
|
|
|
// wbs FIFO
|
// wbs FIFO
|
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
|
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
|
assign a_wr = (wbs==wbs_adr) ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
|
assign a_wr = (wbs==wbs_adr) ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
|
(wbs==wbs_data) ? wbs_we_i & wbs_stb_i & !a_fifo_full :
|
(wbs==wbs_data) ? wbs_we_i & wbs_stb_i & !a_fifo_full :
|
1'b0;
|
1'b0;
|
assign a_rd = !a_fifo_empty;
|
assign a_rd = !a_fifo_empty;
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
if (wbs_rst)
|
if (wbs_rst)
|
a_rd_reg <= 1'b0;
|
a_rd_reg <= 1'b0;
|
else
|
else
|
a_rd_reg <= a_rd;
|
a_rd_reg <= a_rd;
|
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
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assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
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|
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assign wbs_dat_o = a_q[35:4];
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assign wbs_dat_o = a_q[35:4];
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|
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always @ (posedge wbs_clk or posedge wbs_rst)
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always @ (posedge wbs_clk or posedge wbs_rst)
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if (wbs_rst)
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if (wbs_rst)
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wbs_bte_reg <= 2'b00;
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wbs_bte_reg <= 2'b00;
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else
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else
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wbs_bte_reg <= wbs_bte_i;
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wbs_bte_reg <= wbs_bte_i;
|
|
|
// wbm FIFO
|
// wbm FIFO
|
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
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assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
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always @ (posedge wbm_clk or posedge wbm_rst)
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
if (wbm_rst)
|
if (wbm_rst)
|
wbm_eoc <= 1'b0;
|
wbm_eoc <= 1'b0;
|
else
|
else
|
if (wbm==wbm_adr0 & !b_fifo_empty)
|
if (wbm==wbm_adr0 & !b_fifo_empty)
|
wbm_eoc <= b_q[`BTE] == linear;
|
wbm_eoc <= b_q[`BTE] == linear;
|
else if (wbm_eoc_alert & wbm_ack_i)
|
else if (wbm_eoc_alert & wbm_ack_i)
|
wbm_eoc <= 1'b1;
|
wbm_eoc <= 1'b1;
|
|
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
if (wbm_rst)
|
if (wbm_rst)
|
wbm <= wbm_adr0;
|
wbm <= wbm_adr0;
|
else
|
else
|
/*
|
/*
|
if ((wbm==wbm_adr0 & !b_fifo_empty) |
|
if ((wbm==wbm_adr0 & !b_fifo_empty) |
|
(wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
|
(wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
|
(wbm==wbm_adr1 & !wbm_we_o) |
|
(wbm==wbm_adr1 & !wbm_we_o) |
|
(wbm==wbm_data & wbm_ack_i & wbm_eoc))
|
(wbm==wbm_data & wbm_ack_i & wbm_eoc))
|
wbm <= {wbm[0],!(wbm[1] ^ wbm[0])}; // count sequence 00,01,10
|
wbm <= {wbm[0],!(wbm[1] ^ wbm[0])}; // count sequence 00,01,10
|
*/
|
*/
|
case (wbm)
|
case (wbm)
|
wbm_adr0:
|
wbm_adr0:
|
if (!b_fifo_empty)
|
if (!b_fifo_empty)
|
wbm <= wbm_adr1;
|
wbm <= wbm_adr1;
|
wbm_adr1:
|
wbm_adr1:
|
if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
|
if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
|
wbm <= wbm_data;
|
wbm <= wbm_data;
|
wbm_data:
|
wbm_data:
|
if (wbm_ack_i & wbm_eoc)
|
if (wbm_ack_i & wbm_eoc)
|
wbm <= wbm_adr0;
|
wbm <= wbm_adr0;
|
else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
|
else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
|
wbm <= wbm_data_wait;
|
wbm <= wbm_data_wait;
|
wbm_data_wait:
|
wbm_data_wait:
|
if (!b_fifo_empty)
|
if (!b_fifo_empty)
|
wbm <= wbm_data;
|
wbm <= wbm_data;
|
endcase
|
endcase
|
|
|
assign b_d = {wbm_dat_i,4'b1111};
|
assign b_d = {wbm_dat_i,4'b1111};
|
assign b_wr = !wbm_we_o & wbm_ack_i;
|
assign b_wr = !wbm_we_o & wbm_ack_i;
|
assign b_rd_adr = (wbm==wbm_adr0 & !b_fifo_empty);
|
assign b_rd_adr = (wbm==wbm_adr0 & !b_fifo_empty);
|
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
|
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
|
(wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
|
(wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
|
(wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
|
(wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
|
1'b0;
|
1'b0;
|
assign b_rd = b_rd_adr | b_rd_data;
|
assign b_rd = b_rd_adr | b_rd_data;
|
|
|
`define MODULE dff
|
`define MODULE dff
|
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
|
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
|
`undef MODULE
|
`undef MODULE
|
`define MODULE dff_ce
|
`define MODULE dff_ce
|
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
|
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
|
`undef MODULE
|
`undef MODULE
|
|
|
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
|
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
|
|
|
`define MODULE cnt_shreg_ce_clear
|
`define MODULE cnt_shreg_ce_clear
|
`BASE`MODULE # ( .length(16))
|
`BASE`MODULE # ( .length(16))
|
`undef MODULE
|
`undef MODULE
|
cnt1 (
|
cnt1 (
|
.cke(wbm_ack_i),
|
.cke(wbm_ack_i),
|
.clear(wbm_eoc),
|
.clear(wbm_eoc),
|
.q(wbm_count),
|
.q(wbm_count),
|
.rst(wbm_rst),
|
.rst(wbm_rst),
|
.clk(wbm_clk));
|
.clk(wbm_clk));
|
|
|
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
|
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
|
assign wbm_stb_o = (wbm==wbm_data);
|
assign wbm_stb_o = (wbm==wbm_data);
|
|
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
if (wbm_rst)
|
if (wbm_rst)
|
{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
|
{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
|
else begin
|
else begin
|
if (wbm==wbm_adr0 & !b_fifo_empty)
|
if (wbm==wbm_adr0 & !b_fifo_empty)
|
{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
|
{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
|
else if (wbm_eoc_alert & wbm_ack_i)
|
else if (wbm_eoc_alert & wbm_ack_i)
|
wbm_cti_o <= endofburst;
|
wbm_cti_o <= endofburst;
|
end
|
end
|
|
|
//async_fifo_dw_simplex_top
|
//async_fifo_dw_simplex_top
|
`define MODULE fifo_2r2w_async_simplex
|
`define MODULE fifo_2r2w_async_simplex
|
`BASE`MODULE
|
`BASE`MODULE
|
`undef MODULE
|
`undef MODULE
|
# ( .data_width(36), .addr_width(addr_width))
|
# ( .data_width(36), .addr_width(addr_width))
|
fifo (
|
fifo (
|
// a side
|
// a side
|
.a_d(a_d),
|
.a_d(a_d),
|
.a_wr(a_wr),
|
.a_wr(a_wr),
|
.a_fifo_full(a_fifo_full),
|
.a_fifo_full(a_fifo_full),
|
.a_q(a_q),
|
.a_q(a_q),
|
.a_rd(a_rd),
|
.a_rd(a_rd),
|
.a_fifo_empty(a_fifo_empty),
|
.a_fifo_empty(a_fifo_empty),
|
.a_clk(wbs_clk),
|
.a_clk(wbs_clk),
|
.a_rst(wbs_rst),
|
.a_rst(wbs_rst),
|
// b side
|
// b side
|
.b_d(b_d),
|
.b_d(b_d),
|
.b_wr(b_wr),
|
.b_wr(b_wr),
|
.b_fifo_full(b_fifo_full),
|
.b_fifo_full(b_fifo_full),
|
.b_q(b_q),
|
.b_q(b_q),
|
.b_rd(b_rd),
|
.b_rd(b_rd),
|
.b_fifo_empty(b_fifo_empty),
|
.b_fifo_empty(b_fifo_empty),
|
.b_clk(wbm_clk),
|
.b_clk(wbm_clk),
|
.b_rst(wbm_rst)
|
.b_rst(wbm_rst)
|
);
|
);
|
|
|
endmodule
|
endmodule
|
`undef WE
|
`undef WE
|
`undef BTE
|
`undef BTE
|
`undef CTI
|
`undef CTI
|
`endif
|
`endif
|
|
|
`ifdef WB3_ARBITER_TYPE1
|
`ifdef WB3_ARBITER_TYPE1
|
`define MODULE wb3_arbiter_type1
|
`define MODULE wb3_arbiter_type1
|
module `BASE`MODULE (
|
module `BASE`MODULE (
|
`undef MODULE
|
`undef MODULE
|
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
|
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
|
wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
|
wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
|
wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
|
wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
|
wb_clk, wb_rst
|
wb_clk, wb_rst
|
);
|
);
|
|
|
parameter nr_of_ports = 3;
|
parameter nr_of_ports = 3;
|
parameter adr_size = 26;
|
parameter adr_size = 26;
|
parameter adr_lo = 2;
|
parameter adr_lo = 2;
|
parameter dat_size = 32;
|
parameter dat_size = 32;
|
parameter sel_size = dat_size/8;
|
parameter sel_size = dat_size/8;
|
|
|
localparam aw = (adr_size - adr_lo) * nr_of_ports;
|
localparam aw = (adr_size - adr_lo) * nr_of_ports;
|
localparam dw = dat_size * nr_of_ports;
|
localparam dw = dat_size * nr_of_ports;
|
localparam sw = sel_size * nr_of_ports;
|
localparam sw = sel_size * nr_of_ports;
|
localparam cw = 3 * nr_of_ports;
|
localparam cw = 3 * nr_of_ports;
|
localparam bw = 2 * nr_of_ports;
|
localparam bw = 2 * nr_of_ports;
|
|
|
input [dw-1:0] wbm_dat_o;
|
input [dw-1:0] wbm_dat_o;
|
input [aw-1:0] wbm_adr_o;
|
input [aw-1:0] wbm_adr_o;
|
input [sw-1:0] wbm_sel_o;
|
input [sw-1:0] wbm_sel_o;
|
input [cw-1:0] wbm_cti_o;
|
input [cw-1:0] wbm_cti_o;
|
input [bw-1:0] wbm_bte_o;
|
input [bw-1:0] wbm_bte_o;
|
input [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
|
input [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
|
output [dw-1:0] wbm_dat_i;
|
output [dw-1:0] wbm_dat_i;
|
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
|
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
|
|
|
output [dat_size-1:0] wbs_dat_i;
|
output [dat_size-1:0] wbs_dat_i;
|
output [adr_size-1:adr_lo] wbs_adr_i;
|
output [adr_size-1:adr_lo] wbs_adr_i;
|
output [sel_size-1:0] wbs_sel_i;
|
output [sel_size-1:0] wbs_sel_i;
|
output [2:0] wbs_cti_i;
|
output [2:0] wbs_cti_i;
|
output [1:0] wbs_bte_i;
|
output [1:0] wbs_bte_i;
|
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
|
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
|
input [dat_size-1:0] wbs_dat_o;
|
input [dat_size-1:0] wbs_dat_o;
|
input wbs_ack_o, wbs_err_o, wbs_rty_o;
|
input wbs_ack_o, wbs_err_o, wbs_rty_o;
|
|
|
input wb_clk, wb_rst;
|
input wb_clk, wb_rst;
|
|
|
reg [nr_of_ports-1:0] select;
|
reg [nr_of_ports-1:0] select;
|
wire [nr_of_ports-1:0] state;
|
wire [nr_of_ports-1:0] state;
|
wire [nr_of_ports-1:0] eoc; // end-of-cycle
|
wire [nr_of_ports-1:0] eoc; // end-of-cycle
|
wire [nr_of_ports-1:0] sel;
|
wire [nr_of_ports-1:0] sel;
|
wire idle;
|
wire idle;
|
|
|
genvar i;
|
genvar i;
|
|
|
assign idle = !(|state);
|
assign idle = !(|state);
|
|
|
generate
|
generate
|
if (nr_of_ports == 2) begin
|
if (nr_of_ports == 2) begin
|
|
|
wire [2:0] wbm1_cti_o, wbm0_cti_o;
|
wire [2:0] wbm1_cti_o, wbm0_cti_o;
|
|
|
assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
|
|
//assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
|
//assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
|
|
|
always @ (idle or wbm_cyc_o)
|
always @ (idle or wbm_cyc_o)
|
if (idle)
|
if (idle)
|
casex (wbm_cyc_o)
|
casex (wbm_cyc_o)
|
2'b1x : select = 2'b10;
|
2'b1x : select = 2'b10;
|
2'b01 : select = 2'b01;
|
2'b01 : select = 2'b01;
|
default : select = {nr_of_ports{1'b0}};
|
default : select = {nr_of_ports{1'b0}};
|
endcase
|
endcase
|
else
|
else
|
select = {nr_of_ports{1'b0}};
|
select = {nr_of_ports{1'b0}};
|
|
|
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
generate
|
generate
|
if (nr_of_ports == 3) begin
|
if (nr_of_ports == 3) begin
|
|
|
wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
|
wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
|
|
|
assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
|
|
always @ (idle or wbm_cyc_o)
|
always @ (idle or wbm_cyc_o)
|
if (idle)
|
if (idle)
|
casex (wbm_cyc_o)
|
casex (wbm_cyc_o)
|
3'b1xx : select = 3'b100;
|
3'b1xx : select = 3'b100;
|
3'b01x : select = 3'b010;
|
3'b01x : select = 3'b010;
|
3'b001 : select = 3'b001;
|
3'b001 : select = 3'b001;
|
default : select = {nr_of_ports{1'b0}};
|
default : select = {nr_of_ports{1'b0}};
|
endcase
|
endcase
|
else
|
else
|
select = {nr_of_ports{1'b0}};
|
select = {nr_of_ports{1'b0}};
|
|
|
// assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
|
// assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
|
assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
|
assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
|
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
generate
|
generate
|
if (nr_of_ports == 4) begin
|
if (nr_of_ports == 4) begin
|
|
|
wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
|
wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
|
|
|
assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
|
|
//assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
|
//assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
|
|
|
always @ (idle or wbm_cyc_o)
|
always @ (idle or wbm_cyc_o)
|
if (idle)
|
if (idle)
|
casex (wbm_cyc_o)
|
casex (wbm_cyc_o)
|
4'b1xxx : select = 4'b1000;
|
4'b1xxx : select = 4'b1000;
|
4'b01xx : select = 4'b0100;
|
4'b01xx : select = 4'b0100;
|
4'b001x : select = 4'b0010;
|
4'b001x : select = 4'b0010;
|
4'b0001 : select = 4'b0001;
|
4'b0001 : select = 4'b0001;
|
default : select = {nr_of_ports{1'b0}};
|
default : select = {nr_of_ports{1'b0}};
|
endcase
|
endcase
|
else
|
else
|
select = {nr_of_ports{1'b0}};
|
select = {nr_of_ports{1'b0}};
|
|
|
assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
|
assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
|
assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
|
assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
|
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
generate
|
generate
|
if (nr_of_ports == 5) begin
|
if (nr_of_ports == 5) begin
|
|
|
wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
|
wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
|
|
|
assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
|
|
//assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
|
//assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
|
|
|
always @ (idle or wbm_cyc_o)
|
always @ (idle or wbm_cyc_o)
|
if (idle)
|
if (idle)
|
casex (wbm_cyc_o)
|
casex (wbm_cyc_o)
|
5'b1xxxx : select = 5'b10000;
|
5'b1xxxx : select = 5'b10000;
|
5'b01xxx : select = 5'b01000;
|
5'b01xxx : select = 5'b01000;
|
5'b001xx : select = 5'b00100;
|
5'b001xx : select = 5'b00100;
|
5'b0001x : select = 5'b00010;
|
5'b0001x : select = 5'b00010;
|
5'b00001 : select = 5'b00001;
|
5'b00001 : select = 5'b00001;
|
default : select = {nr_of_ports{1'b0}};
|
default : select = {nr_of_ports{1'b0}};
|
endcase
|
endcase
|
else
|
else
|
select = {nr_of_ports{1'b0}};
|
select = {nr_of_ports{1'b0}};
|
|
|
assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
|
assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
|
assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
|
assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
|
assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
|
assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
|
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
|
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
generate
|
generate
|
for (i=0;i<nr_of_ports;i=i+1) begin
|
for (i=0;i<nr_of_ports;i=i+1) begin
|
`define MODULE spr
|
`define MODULE spr
|
`BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
|
`BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
|
`undef MODULE
|
`undef MODULE
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
assign sel = select | state;
|
assign sel = select | state;
|
|
|
`define MODULE mux_andor
|
`define MODULE mux_andor
|
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
|
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
|
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
|
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
|
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
|
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
|
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
|
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
|
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
|
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
|
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
|
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
|
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
|
`BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
|
`undef MODULE
|
`undef MODULE
|
assign wbs_cyc_i = |sel;
|
assign wbs_cyc_i = |sel;
|
|
|
assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
|
assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
|
assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
|
assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
|
assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
|
assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
|
assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
|
assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
|
|
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
`ifdef WB_B3_RAM_BE
|
`ifdef WB_B3_RAM_BE
|
// WB RAM with byte enable
|
// WB RAM with byte enable
|
`define MODULE wb_b3_ram_be
|
`define MODULE wb_b3_ram_be
|
module `BASE`MODULE (
|
module `BASE`MODULE (
|
`undef MODULE
|
`undef MODULE
|
wb_dat_i, wb_adr_i, wb_cti_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
|
wb_dat_i, wb_adr_i, wb_cti_i, wb_bte_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
|
wb_dat_o, wb_ack_o, wb_clk, wb_rst);
|
wb_dat_o, wb_ack_o, wb_clk, wb_rst);
|
|
|
parameter nr_of_ports = 3;
|
parameter nr_of_ports = 3;
|
parameter wb_arbiter_type = 1;
|
parameter wb_arbiter_type = 1;
|
parameter adr_size = 26;
|
parameter adr_size = 26;
|
parameter adr_lo = 2;
|
parameter adr_lo = 2;
|
parameter dat_size = 32;
|
parameter dat_size = 32;
|
parameter memory_init = 1;
|
parameter memory_init = 1;
|
parameter memory_file = "vl_ram.vmem";
|
parameter memory_file = "vl_ram.vmem";
|
|
|
localparam aw = (adr_size - adr_lo) * nr_of_ports;
|
localparam aw = (adr_size - adr_lo) * nr_of_ports;
|
localparam dw = dat_size * nr_of_ports;
|
localparam dw = dat_size * nr_of_ports;
|
localparam sw = dat_size/8 * nr_of_ports;
|
localparam sw = dat_size/8 * nr_of_ports;
|
localparam cw = 3 * nr_of_ports;
|
localparam cw = 3 * nr_of_ports;
|
localparam bw = 2 * nr_of_ports;
|
localparam bw = 2 * nr_of_ports;
|
|
|
input [dw-1:0] wb_dat_i;
|
input [dw-1:0] wb_dat_i;
|
input [aw-1:0] wb_adr_i;
|
input [aw-1:0] wb_adr_i;
|
input [cw-1:0] wb_cti_i;
|
input [cw-1:0] wb_cti_i;
|
|
input [bw-1:0] wb_bte_i;
|
input [sw-1:0] wb_sel_i;
|
input [sw-1:0] wb_sel_i;
|
input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i;
|
input [nr_of_ports-1:0] wb_we_i, wb_stb_i, wb_cyc_i;
|
output [dw-1:0] wb_dat_o;
|
output [dw-1:0] wb_dat_o;
|
reg [dw-1:0] wb_dat_o;
|
reg [dw-1:0] wb_dat_o;
|
output wb_ack_o;
|
output wb_ack_o;
|
reg wb_ack_o;
|
reg wb_ack_o;
|
input wb_clk, wb_rst;
|
input wb_clk, wb_rst;
|
|
|
wire [sw-1:0] cke;
|
wire [sw-1:0] cke;
|
|
|
// local wb slave
|
// local wb slave
|
wire [dat_size-1:0] wbs_dat_i;
|
wire [dat_size-1:0] wbs_dat_i;
|
wire [adr_size-1:0] wbs_adr_i;
|
wire [adr_size-1:0] wbs_adr_i;
|
wire [2:0] wbs_cti_i;
|
wire [2:0] wbs_cti_i;
|
|
wire [1:0] wbs_bte_i;
|
wire [(dat_size/8)-1:0] wbs_sel_i;
|
wire [(dat_size/8)-1:0] wbs_sel_i;
|
wire wbs_we_i, wbs_stb_i, wbs_cyc_i;
|
wire wbs_we_i, wbs_stb_i, wbs_cyc_i;
|
wire [dat_size-1:0] wbs_dat_o;
|
wire [dat_size-1:0] wbs_dat_o;
|
reg wbs_ack_o;
|
reg wbs_ack_o;
|
|
|
generate
|
generate
|
if (nr_of_ports == 1) begin
|
if (nr_of_ports == 1) begin
|
assign wbs_dat_i = wb_dat_i;
|
assign wbs_dat_i = wb_dat_i;
|
assign wbs_adr_i = wb_adr_i;
|
assign wbs_adr_i = wb_adr_i;
|
assign wbs_cti_i = wb_cti_i;
|
assign wbs_cti_i = wb_cti_i;
|
assign wbs_sel_i = wb_sel_i;
|
assign wbs_sel_i = wb_sel_i;
|
assign wbs_we_i = wb_we_i;
|
assign wbs_we_i = wb_we_i;
|
assign wbs_stb_i = wb_stb_i;
|
assign wbs_stb_i = wb_stb_i;
|
assign wbs_cyc_i = wb_cyc_i;
|
assign wbs_cyc_i = wb_cyc_i;
|
assign wb_dat_o = wbs_dat_o;
|
assign wb_dat_o = wbs_dat_o;
|
assign wb_ack_o = wbs_ack_o;
|
assign wb_ack_o = wbs_ack_o;
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
generate
|
generate
|
if (nr_of_ports > 1 & wb_arbiter_type == 1) begin
|
if (nr_of_ports > 1 & wb_arbiter_type == 1) begin
|
`define MODULE wb3_arbiter_type1
|
`define MODULE wb3_arbiter_type1
|
`BASE`MODULE wb_arbiter0(
|
`BASE`MODULE wb_arbiter0(
|
`undef MODULE
|
`undef MODULE
|
.wbm_dat_o(wb_dat_i),
|
.wbm_dat_o(wb_dat_i),
|
.wbm_adr_o(wb_adr_i),
|
.wbm_adr_o(wb_adr_i),
|
.wbm_sel_o(wb_sel_i),
|
.wbm_sel_o(wb_sel_i),
|
.wbm_cti_o(wb_cti_i),
|
.wbm_cti_o(wb_cti_i),
|
.wbm_bte_o(wb_bte_i),
|
.wbm_bte_o(wb_bte_i),
|
.wbm_we_o(wb_we_i),
|
.wbm_we_o(wb_we_i),
|
.wbm_stb_o(wb_stb_i),
|
.wbm_stb_o(wb_stb_i),
|
.wbm_cyc_o(wb_cyc_i),
|
.wbm_cyc_o(wb_cyc_i),
|
.wbm_dat_i(wb_dat_o),
|
.wbm_dat_i(wb_dat_o),
|
.wbm_ack_i(wb_ack_o),
|
.wbm_ack_i(wb_ack_o),
|
.wbm_err_i(),
|
.wbm_err_i(),
|
.wbm_rty_i(),
|
.wbm_rty_i(),
|
.wbs_dat_i(wbs_dat_i),
|
.wbs_dat_i(wbs_dat_i),
|
.wbs_adr_i(wbs_adr_i),
|
.wbs_adr_i(wbs_adr_i),
|
.wbs_sel_i(wbs_sel_i),
|
.wbs_sel_i(wbs_sel_i),
|
.wbs_cti_i(wbs_cti_i),
|
.wbs_cti_i(wbs_cti_i),
|
.wbs_bte_i(wbs_bte_i),
|
.wbs_bte_i(wbs_bte_i),
|
.wbs_we_i(wbs_we_i),
|
.wbs_we_i(wbs_we_i),
|
.wbs_stb_i(wbs_stb_i),
|
.wbs_stb_i(wbs_stb_i),
|
.wbs_cyc_i(wbs_cyc_i),
|
.wbs_cyc_i(wbs_cyc_i),
|
.wbs_dat_o(wbs_dat_o),
|
.wbs_dat_o(wbs_dat_o),
|
.wbs_ack_o(wbs_ack_o),
|
.wbs_ack_o(wbs_ack_o),
|
.wbs_err_o(1'b0),
|
.wbs_err_o(1'b0),
|
.wbs_rty_o(1'b0),
|
.wbs_rty_o(1'b0),
|
.wb_clk(wb_clk),
|
.wb_clk(wb_clk),
|
.wb_rst(wb_rst)
|
.wb_rst(wb_rst)
|
);
|
);
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
`define MODULE ram_be
|
`define MODULE ram_be
|
`BASE`MODULE # (
|
`BASE`MODULE # (
|
.data_width(dat_size),
|
.data_width(dat_size),
|
.addr_width(adr_size),
|
.addr_width(adr_size),
|
.memory_init(1),
|
.memory_init(1),
|
.memory_file("memory_file"))
|
.memory_file("memory_file"))
|
ram0(
|
ram0(
|
`undef MODULE
|
`undef MODULE
|
.d(wbs_dat_i),
|
.d(wbs_dat_i),
|
.adr(wbs_adr_i[adr_size-1:2]),
|
.adr(wbs_adr_i[adr_size-1:2]),
|
.be(wbs_sel_i),
|
.be(wbs_sel_i),
|
.we(wbs_we_i),
|
.we(wbs_we_i),
|
.q(wbs_dat_o),
|
.q(wbs_dat_o),
|
.clk(wb_clk)
|
.clk(wb_clk)
|
);
|
);
|
|
|
always @ (posedge wb_clk or posedge wb_rst)
|
always @ (posedge wb_clk or posedge wb_rst)
|
if (wb_rst)
|
if (wb_rst)
|
wbs_ack_o <= 1'b0;
|
wbs_ack_o <= 1'b0;
|
else
|
else
|
if (wbs_cti_i==3'b000 | wbs_cti_i==3'b111)
|
if (wbs_cti_i==3'b000 | wbs_cti_i==3'b111)
|
wbs_ack_o <= wbs_stb_i & wbs_cyc_i & !wbs_ack_o;
|
wbs_ack_o <= wbs_stb_i & wbs_cyc_i & !wbs_ack_o;
|
else
|
else
|
wbs_ack_o <= wbs_stb_i & wbs_cyc_i;
|
wbs_ack_o <= wbs_stb_i & wbs_cyc_i;
|
|
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
`ifdef WB_B4_RAM_BE
|
`ifdef WB_B4_RAM_BE
|
// WB RAM with byte enable
|
// WB RAM with byte enable
|
`define MODULE wb_b4_ram_be
|
`define MODULE wb_b4_ram_be
|
module `BASE`MODULE (
|
module `BASE`MODULE (
|
`undef MODULE
|
`undef MODULE
|
wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
|
wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
|
wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
|
wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
|
|
|
parameter dat_width = 32;
|
parameter dat_width = 32;
|
parameter adr_width = 8;
|
parameter adr_width = 8;
|
|
|
input [dat_width-1:0] wb_dat_i;
|
input [dat_width-1:0] wb_dat_i;
|
input [adr_width-1:0] wb_adr_i;
|
input [adr_width-1:0] wb_adr_i;
|
input [dat_width/8-1:0] wb_sel_i;
|
input [dat_width/8-1:0] wb_sel_i;
|
input wb_we_i, wb_stb_i, wb_cyc_i;
|
input wb_we_i, wb_stb_i, wb_cyc_i;
|
output [dat_width-1:0] wb_dat_o;
|
output [dat_width-1:0] wb_dat_o;
|
reg [dat_width-1:0] wb_dat_o;
|
reg [dat_width-1:0] wb_dat_o;
|
output wb_stall_o;
|
output wb_stall_o;
|
output wb_ack_o;
|
output wb_ack_o;
|
reg wb_ack_o;
|
reg wb_ack_o;
|
input wb_clk, wb_rst;
|
input wb_clk, wb_rst;
|
|
|
wire [dat_width/8-1:0] cke;
|
wire [dat_width/8-1:0] cke;
|
|
|
generate
|
generate
|
if (dat_width==32) begin
|
if (dat_width==32) begin
|
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
|
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
|
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
|
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
|
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
|
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
|
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
|
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
|
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}};
|
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}};
|
always @ (posedge wb_clk)
|
always @ (posedge wb_clk)
|
begin
|
begin
|
if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
|
if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
|
if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
|
if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
|
if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
|
if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
|
if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
|
if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
|
end
|
end
|
always @ (posedge wb_clk or posedge wb_rst)
|
always @ (posedge wb_clk or posedge wb_rst)
|
begin
|
begin
|
if (wb_rst)
|
if (wb_rst)
|
wb_dat_o <= 32'h0;
|
wb_dat_o <= 32'h0;
|
else
|
else
|
wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
|
wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
always @ (posedge wb_clk or posedge wb_rst)
|
always @ (posedge wb_clk or posedge wb_rst)
|
if (wb_rst)
|
if (wb_rst)
|
wb_ack_o <= 1'b0;
|
wb_ack_o <= 1'b0;
|
else
|
else
|
wb_ack_o <= wb_stb_i & wb_cyc_i;
|
wb_ack_o <= wb_stb_i & wb_cyc_i;
|
|
|
assign wb_stall_o = 1'b0;
|
assign wb_stall_o = 1'b0;
|
|
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
`ifdef WB_B4_ROM
|
`ifdef WB_B4_ROM
|
// WB ROM
|
// WB ROM
|
`define MODULE wb_b4_rom
|
`define MODULE wb_b4_rom
|
module `BASE`MODULE (
|
module `BASE`MODULE (
|
`undef MODULE
|
`undef MODULE
|
wb_adr_i, wb_stb_i, wb_cyc_i,
|
wb_adr_i, wb_stb_i, wb_cyc_i,
|
wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
|
wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
|
|
|
parameter dat_width = 32;
|
parameter dat_width = 32;
|
parameter dat_default = 32'h15000000;
|
parameter dat_default = 32'h15000000;
|
parameter adr_width = 32;
|
parameter adr_width = 32;
|
|
|
/*
|
/*
|
//E2_ifndef ROM
|
//E2_ifndef ROM
|
//E2_define ROM "rom.v"
|
//E2_define ROM "rom.v"
|
//E2_endif
|
//E2_endif
|
*/
|
*/
|
input [adr_width-1:2] wb_adr_i;
|
input [adr_width-1:2] wb_adr_i;
|
input wb_stb_i;
|
input wb_stb_i;
|
input wb_cyc_i;
|
input wb_cyc_i;
|
output [dat_width-1:0] wb_dat_o;
|
output [dat_width-1:0] wb_dat_o;
|
reg [dat_width-1:0] wb_dat_o;
|
reg [dat_width-1:0] wb_dat_o;
|
output wb_ack_o;
|
output wb_ack_o;
|
reg wb_ack_o;
|
reg wb_ack_o;
|
output stall_o;
|
output stall_o;
|
input wb_clk;
|
input wb_clk;
|
input wb_rst;
|
input wb_rst;
|
|
|
always @ (posedge wb_clk or posedge wb_rst)
|
always @ (posedge wb_clk or posedge wb_rst)
|
if (wb_rst)
|
if (wb_rst)
|
wb_dat_o <= {dat_width{1'b0}};
|
wb_dat_o <= {dat_width{1'b0}};
|
else
|
else
|
case (wb_adr_i[adr_width-1:2])
|
case (wb_adr_i[adr_width-1:2])
|
//E2_ifdef ROM
|
//E2_ifdef ROM
|
//E2_include `ROM
|
//E2_include `ROM
|
//E2_endif
|
//E2_endif
|
default:
|
default:
|
wb_dat_o <= dat_default;
|
wb_dat_o <= dat_default;
|
|
|
endcase // case (wb_adr_i)
|
endcase // case (wb_adr_i)
|
|
|
|
|
always @ (posedge wb_clk or posedge wb_rst)
|
always @ (posedge wb_clk or posedge wb_rst)
|
if (wb_rst)
|
if (wb_rst)
|
wb_ack_o <= 1'b0;
|
wb_ack_o <= 1'b0;
|
else
|
else
|
wb_ack_o <= wb_stb_i & wb_cyc_i;
|
wb_ack_o <= wb_stb_i & wb_cyc_i;
|
|
|
assign stall_o = 1'b0;
|
assign stall_o = 1'b0;
|
|
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
|
|
`ifdef WB_BOOT_ROM
|
`ifdef WB_BOOT_ROM
|
// WB ROM
|
// WB ROM
|
`define MODULE wb_boot_rom
|
`define MODULE wb_boot_rom
|
module `BASE`MODULE (
|
module `BASE`MODULE (
|
`undef MODULE
|
`undef MODULE
|
wb_adr_i, wb_stb_i, wb_cyc_i,
|
wb_adr_i, wb_stb_i, wb_cyc_i,
|
wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
|
wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
|
|
|
parameter adr_hi = 31;
|
parameter adr_hi = 31;
|
parameter adr_lo = 28;
|
parameter adr_lo = 28;
|
parameter adr_sel = 4'hf;
|
parameter adr_sel = 4'hf;
|
parameter addr_width = 5;
|
parameter addr_width = 5;
|
/*
|
/*
|
//E2_ifndef BOOT_ROM
|
//E2_ifndef BOOT_ROM
|
//E2_define BOOT_ROM "boot_rom.v"
|
//E2_define BOOT_ROM "boot_rom.v"
|
//E2_endif
|
//E2_endif
|
*/
|
*/
|
input [adr_hi:2] wb_adr_i;
|
input [adr_hi:2] wb_adr_i;
|
input wb_stb_i;
|
input wb_stb_i;
|
input wb_cyc_i;
|
input wb_cyc_i;
|
output [31:0] wb_dat_o;
|
output [31:0] wb_dat_o;
|
output wb_ack_o;
|
output wb_ack_o;
|
output hit_o;
|
output hit_o;
|
input wb_clk;
|
input wb_clk;
|
input wb_rst;
|
input wb_rst;
|
|
|
wire hit;
|
wire hit;
|
reg [31:0] wb_dat;
|
reg [31:0] wb_dat;
|
reg wb_ack;
|
reg wb_ack;
|
|
|
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
|
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
|
|
|
always @ (posedge wb_clk or posedge wb_rst)
|
always @ (posedge wb_clk or posedge wb_rst)
|
if (wb_rst)
|
if (wb_rst)
|
wb_dat <= 32'h15000000;
|
wb_dat <= 32'h15000000;
|
else
|
else
|
case (wb_adr_i[addr_width-1:2])
|
case (wb_adr_i[addr_width-1:2])
|
//E2_ifdef BOOT_ROM
|
//E2_ifdef BOOT_ROM
|
//E2_include `BOOT_ROM
|
//E2_include `BOOT_ROM
|
//E2_endif
|
//E2_endif
|
/*
|
/*
|
// Zero r0 and jump to 0x00000100
|
// Zero r0 and jump to 0x00000100
|
0 : wb_dat <= 32'h18000000;
|
0 : wb_dat <= 32'h18000000;
|
1 : wb_dat <= 32'hA8200000;
|
1 : wb_dat <= 32'hA8200000;
|
2 : wb_dat <= 32'hA8C00100;
|
2 : wb_dat <= 32'hA8C00100;
|
3 : wb_dat <= 32'h44003000;
|
3 : wb_dat <= 32'h44003000;
|
4 : wb_dat <= 32'h15000000;
|
4 : wb_dat <= 32'h15000000;
|
*/
|
*/
|
default:
|
default:
|
wb_dat <= 32'h00000000;
|
wb_dat <= 32'h00000000;
|
|
|
endcase // case (wb_adr_i)
|
endcase // case (wb_adr_i)
|
|
|
|
|
always @ (posedge wb_clk or posedge wb_rst)
|
always @ (posedge wb_clk or posedge wb_rst)
|
if (wb_rst)
|
if (wb_rst)
|
wb_ack <= 1'b0;
|
wb_ack <= 1'b0;
|
else
|
else
|
wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
|
wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
|
|
|
assign hit_o = hit;
|
assign hit_o = hit;
|
assign wb_dat_o = wb_dat & {32{wb_ack}};
|
assign wb_dat_o = wb_dat & {32{wb_ack}};
|
assign wb_ack_o = wb_ack;
|
assign wb_ack_o = wb_ack;
|
|
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
`ifdef WB_DPRAM
|
`ifdef WB_DPRAM
|
`define MODULE wb_dpram
|
`define MODULE wb_dpram
|
module `BASE`MODULE (
|
module `BASE`MODULE (
|
`undef MODULE
|
`undef MODULE
|
// wishbone slave side a
|
// wishbone slave side a
|
wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
|
wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
|
wbsa_clk, wbsa_rst,
|
wbsa_clk, wbsa_rst,
|
// wishbone slave side a
|
// wishbone slave side a
|
wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
|
wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
|
wbsb_clk, wbsb_rst);
|
wbsb_clk, wbsb_rst);
|
|
|
parameter data_width = 32;
|
parameter data_width = 32;
|
parameter addr_width = 8;
|
parameter addr_width = 8;
|
|
|
parameter dat_o_mask_a = 1;
|
parameter dat_o_mask_a = 1;
|
parameter dat_o_mask_b = 1;
|
parameter dat_o_mask_b = 1;
|
|
|
input [31:0] wbsa_dat_i;
|
input [31:0] wbsa_dat_i;
|
input [addr_width-1:2] wbsa_adr_i;
|
input [addr_width-1:2] wbsa_adr_i;
|
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
|
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
|
output [31:0] wbsa_dat_o;
|
output [31:0] wbsa_dat_o;
|
output wbsa_ack_o;
|
output wbsa_ack_o;
|
input wbsa_clk, wbsa_rst;
|
input wbsa_clk, wbsa_rst;
|
|
|
input [31:0] wbsb_dat_i;
|
input [31:0] wbsb_dat_i;
|
input [addr_width-1:2] wbsb_adr_i;
|
input [addr_width-1:2] wbsb_adr_i;
|
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
|
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
|
output [31:0] wbsb_dat_o;
|
output [31:0] wbsb_dat_o;
|
output wbsb_ack_o;
|
output wbsb_ack_o;
|
input wbsb_clk, wbsb_rst;
|
input wbsb_clk, wbsb_rst;
|
|
|
wire wbsa_dat_tmp, wbsb_dat_tmp;
|
wire wbsa_dat_tmp, wbsb_dat_tmp;
|
|
|
`define MODULE dpram_2r2w
|
`define MODULE dpram_2r2w
|
`BASE`MODULE # (
|
`BASE`MODULE # (
|
`undef MODULE
|
`undef MODULE
|
.data_width(data_width), .addr_width(addr_width) )
|
.data_width(data_width), .addr_width(addr_width) )
|
dpram0(
|
dpram0(
|
.d_a(wbsa_dat_i),
|
.d_a(wbsa_dat_i),
|
.q_a(wbsa_dat_tmp),
|
.q_a(wbsa_dat_tmp),
|
.adr_a(wbsa_adr_i),
|
.adr_a(wbsa_adr_i),
|
.we_a(wbsa_we_i),
|
.we_a(wbsa_we_i),
|
.clk_a(wbsa_clk),
|
.clk_a(wbsa_clk),
|
.d_b(wbsb_dat_i),
|
.d_b(wbsb_dat_i),
|
.q_b(wbsb_dat_tmp),
|
.q_b(wbsb_dat_tmp),
|
.adr_b(wbsb_adr_i),
|
.adr_b(wbsb_adr_i),
|
.we_b(wbsb_we_i),
|
.we_b(wbsb_we_i),
|
.clk_b(wbsb_clk) );
|
.clk_b(wbsb_clk) );
|
|
|
generate if (dat_o_mask_a==1)
|
generate if (dat_o_mask_a==1)
|
assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
|
assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
|
endgenerate
|
endgenerate
|
generate if (dat_o_mask_a==0)
|
generate if (dat_o_mask_a==0)
|
assign wbsa_dat_o = wbsa_dat_tmp;
|
assign wbsa_dat_o = wbsa_dat_tmp;
|
endgenerate
|
endgenerate
|
|
|
generate if (dat_o_mask_b==1)
|
generate if (dat_o_mask_b==1)
|
assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
|
assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
|
endgenerate
|
endgenerate
|
generate if (dat_o_mask_b==0)
|
generate if (dat_o_mask_b==0)
|
assign wbsb_dat_o = wbsb_dat_tmp;
|
assign wbsb_dat_o = wbsb_dat_tmp;
|
endgenerate
|
endgenerate
|
|
|
`define MODULE spr
|
`define MODULE spr
|
`BASE`MODULE ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
|
`BASE`MODULE ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
|
`BASE`MODULE ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
|
`BASE`MODULE ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
|
`undef MODULE
|
`undef MODULE
|
|
|
endmodule
|
endmodule
|
`endif
|
`endif
|
|
|
