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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [wb.v] - Diff between revs 71 and 72

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Rev 71 Rev 72
Line 608... Line 608...
reg wbs_ack_o;
reg wbs_ack_o;
 
 
`define MODULE ram_be
`define MODULE ram_be
`BASE`MODULE # (
`BASE`MODULE # (
    .data_width(dat_size),
    .data_width(dat_size),
    .addr_width(adr_size),
    .addr_width(adr_size-2),
    .mem_size(mem_size),
    .mem_size(mem_size),
    .memory_init(memory_init),
    .memory_init(memory_init),
    .memory_file(memory_file))
    .memory_file(memory_file))
ram0(
ram0(
`undef MODULE
`undef MODULE

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